参数资料
型号: XPC850CZT50BUR2
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 50 MHz, RISC PROCESSOR, PBGA256
封装: PLASTIC, BGA-256
文件页数: 10/76页
文件大小: 825K
代理商: XPC850CZT50BUR2
18
MPC850 (Rev. A/B/C) Hardware Specications
MOTOROLA
Layout Practices
B34
A[6–31] and D[0–31] to CS valid
- as requested by control bit
CST4 in the corresponding word
in the UPM
3.00
6.00
4.00
0.250
50.00
ns
B34a A[6–31] and D[0–31] to CS valid
- as requested by control bit
CST1 in the corresponding word
in the UPM
8.00
13.00
11.00
0.500
50.00
ns
B34b A[6–31] and D[0–31] to CS valid
- as requested by CST2 in the
corresponding word in UPM
13.00
21.00
17.00
0.750
50.00
ns
B35
A[6–31] to CS valid - as
requested by control bit BST4 in
the corresponding word in UPM
3.00
6.00
4.00
0.250
50.00
ns
B35a A[6–31] and D[0–31] to BS valid
- as requested by BST1 in the
corresponding word in the UPM
8.00
13.00
11.00
0.500
50.00
ns
B35b A[6–31] and D[0–31] to BS valid
- as requested by control bit
BST2 in the corresponding word
in the UPM
13.00
21.00
17.00
0.750
50.00
ns
B36
A[6–31] and D[0–31] to GPL
valid - as requested by control
bit GxT4 in the corresponding
word in the UPM
3.00
6.00
4.00
0.250
50.00
ns
B37
UPWAIT valid to CLKOUT falling
edge 10
6.00
6.00
6.00
50.00
ns
B38
CLKOUT falling edge to
UPWAIT valid 10
1.00
1.00
1.00
50.00
ns
B39
AS valid to CLKOUT rising edge
11
7.00
7.00
7.00
50.00
ns
B40
A[6–31], TSIZ[0–1], RD/WR,
BURST, valid to CLKOUT rising
edge.
7.00
7.00
7.00
50.00
ns
B41
TS valid to CLKOUT rising edge
(setup time)
7.00
7.00
7.00
50.00
ns
B42
CLKOUT rising edge to TS valid
(hold time)
2.00
2.00
2.00
50.00
ns
B43
AS negation to memory
controller signals negation
TBD
TBD
50.00
ns
Table 6-6. Bus Operation Timing 1 (continued)
Num
Characteristic
50 MHz
66 MHz
80 MHz
FFACT
Cap Load
(default
50 pF)
Unit
Min
Max
Min
Max
Min
Max
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