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参数资料
| 型号： | XQ4010E-3HQ208N |
| 厂商： | XILINX INC |
| 元件分类： | FPGA |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | FPGA, 400 CLBS, 7000 GATES, 125 MHz, PQFP208 |
| 封装： | PLASTIC, QFP-208 |
| 文件页数： | 7/36页 |
| 文件大小： | 294K |
| 代理商： | XQ4010E-3HQ208N |
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QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
2-57
Product Specification
1-800-255-7778
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XQ4000E IOB Input Switching Characteristic Guidelines (continued)
Symbol
Description
Device
-3
-4
Units
Min
Max
Min
Max
Setup Times (TTL Inputs)(1,2)
TPICK
Pad to clock (IK), no delay
All devices
2.6
-
4.0
-
ns
TPICKD
Pad to clock (IK), with delay
XQ4005E
-
10.9
-
ns
XQ4010E
9.8
-
11.3
-
ns
XQ4013E
10.2
-
11.8
-
ns
XQ4025E
-
14.0
-
ns
Setup Times (CMOS Inputs)(1,2)
TPICKC
Pad to clock (IK), no delay
All devices
3.3
-
6.0
-
ns
TPICKDC Pad to clock (IK), with delay
XQ4005E
-
12.0
-
ns
XQ4010E
10.5
-
13.0
-
ns
XQ4013E
10.9
-
13.5
-
ns
XQ4025E
-
16.0
-
ns
(TTL or CMOS)
TECIK
Clock enable (EC) to clock (IK), no delay
All devices
2.5
-
3.5
-
ns
TECIKD
Clock enable (EC) to clock (IK), with delay
XQ4005E
-
10.4
-
ns
XQ4010E
9.7
-
10.7
-
ns
XQ4013E
10.1
-
11.1
-
ns
XQ4025E
-
14.0
-
ns
Global Set/Reset(3)
TRRI
Delay from GSR net through Q to I1, I2
All devices
-
7.8
-
12.0
ns
TMRW
GSR width
All devices
11.5
-
13.0
-
ns
TMRI
GSR inactive to first active clock (IK) edge
All devices
11.5
-
13.0
-
ns
Notes:
1.
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock
input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
2.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
3.
Timing is based on the XC4005E. For other devices see the XACT timing calculator.
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