参数资料
型号: XR16C2850IJ-F
厂商: Exar Corporation
文件页数: 1/51页
文件大小: 0K
描述: IC UART FIFO 128B 44PLCC
标准包装: 27
特点: *
通道数: 2,DUART
FIFO's: 128 字节
规程: RS232,RS485
电源电压: 2.97 V ~ 5.5 V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 44-LCC(J 形引线)
供应商设备封装: 44-PLCC(16.59x16.59)
包装: 管件
其它名称: 1016-1567-5
XR16C2850IJ-F-ND
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
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XR16C2850
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
NOVEMBER 2005
REV. 2.1.3
GENERAL DESCRIPTION
The XR16C28501 (2850) is an enhanced dual
universal asynchronous receiver and transmitter
(UART). Enhanced features include 128 bytes of TX
and RX FIFOs, programmable TX and RX FIFO
trigger level, FIFO level counters, automatic (RTS/
CTS) hardware and (Xon/Xoff) software flow control,
automatic RS-485 half duplex direction control output
and data rates up to 6.25 Mbps at 5V and 8X
sampling clock. Onboard status registers provide the user
with operational status and data error flags. An internal
loopback capability allows system diagnostics. The 2850
has a full modem interface and can operate at 2.97V
to 5.5V and is pin-to-pin compatible to Exar’s
ST16C2550 and XR16C2750 except the 48-TQFP
package. The 2850 register set is compatible to the
industry standard ST16C2550 and is available in 48-
pin TQFP and 44-pin PLCC packages.
NOTE: 1 Covered by U.S. Patent #5,649,122 and #5,949,787
APPLICATIONS
Portable Appliances
Telecommunication Network Routers
Ethernet Network Routers
Cellular Data Devices
Factory Automation and Process Controls
FEATURES
Added feature in devices with a top mark date code of
"F2 YYWW" and newer:
5V tolerant inputs
0 ns address hold time (TAH)
Pin-to-pin compatible and functionally compatible to
Exar’s ST16C2550 and XR16L2750 and TI’s
TL16C752B in the 48-TQFP package
Pin-alike Exar’s XR16L2750 and ST16C2550 48-
TQFP package but with additional CLK8/16,
CLKSEL and HDCNTL inputs
Two independent UART channels
Register set compatible to 16C550
Up to 6.25 Mbps at 5V, and 4 Mbps at 3.3V
Transmit and Receive FIFOs of 128 bytes
Programmable TX and RX FIFO Trigger Levels
Transmit and Receive FIFO Level Counters
Automatic Hardware (RTS/CTS) Flow Control
Selectable Auto RTS Flow Control Hysteresis
Automatic Software (Xon/Xoff) Flow Control
Auto RS-485 Half-duplex Direction Control
Wireless Infrared (IrDA 1.0) Encoder/Decoder
Full modem interface
Device Identification and Revision
Crystal oscillator or external clock input
Industrial and commercial temperature ranges
48-TQFP and 44-PLCC packages
FIGURE 1. XR16C2850 BLOCK DIAGRAM
XTAL1
XTAL2
Crystal Osc/Buffer
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
8-bit Data
Bus
Interface
UART Channel A
128 Byte TX FIFO
128 Byte RX FIFO
BRG
IR
ENDEC
TX & RX
UART
Regs
2.97V to 5.5V VCC
GND
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
UART Channel B
(same as Channel A)
A2:A0
D7:D0
CSA#
CSB#
INTA
INTB
IOW#
IOR#
Reset
TXRDYA#
TXRDYB#
RXRDYA#
RXRDYB#
CLK8/16
CLKSEL
HDCNTL#
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