参数资料
型号: XR16C2852CJTR-F
厂商: Exar Corporation
文件页数: 43/51页
文件大小: 0K
描述: IC UART FIFO 128B 44PLCC
标准包装: 500
特点: *
通道数: 2,DUART
FIFO's: 128 字节
规程: RS232,RS485
电源电压: 2.97 V ~ 5.5 V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 44-LCC(J 形引线)
供应商设备封装: 44-PLCC(16.59x16.59)
包装: 带卷 (TR)
XR16C2852
xr
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
REV. 2.1.1
48
Revision History
Date
Revision
Description
July 1999
Rev 1.0.0
Initial datasheet.
April 2002
Rev 2.0.0
Changed to standard style format. Internal Registers are described in the order they
are listed in the Internal Register Table. Clarified timing diagrams. Corrected Auto
RTS Hysteresis table. Renamed Rclk (Receive Clock) to Bclk (Baud Clock) and tim-
ing symbols. Added TAH, TCS and OSC.
May 2004
Rev 2.1.0
Changed to single column format. Added device status to ordering information.
Clarified sleep mode conditions. Clarified pin descriptions- changed from using logic
1 and logic 0 to HIGH (VCC) and LOW (GND) for input and output pin descriptions.
Added VOL sink current and VOH source current charts (Figure 14 and Figure 15).
Devices with top mark date code of "F2 YYWW" and newer have 5V tolerant inputs
(except for XTAL1) and have 0 ns address hold time (TAH). DREV register was
updated to 0x06.
February 2005
Rev 2.1.1
Corrected datasheet to show that all inputs are 5V tolerant (including XTAL1) in
devices with top mark date code of "F2 YYWW" and newer.
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