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参数资料
| 型号： | XR16C864IQTR-F |
| 厂商： | Exar Corporation |
| 文件页数： | 4/51页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 128B QUAD 100QFP |
| 标准包装： | 500 |
| 特点： | * |
| 通道数： | 4，QUART |
| FIFO's： | 128 字节 |
| 规程： | RS232，RS485 |
| 电源电压： | 2.97 V ~ 5.5 V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-BQFP |
| 供应商设备封装： | 100-QFP（14x20） |
| 包装： | 带卷 (TR) |
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XR16C864
12
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
REV. 2.2.0
2.8
Direct Memory Access
In this document, Direct Memory Access will not be referred to by its acronym (DMA) to avoid confusion with
DMA Mode (a legacy term) that refers to data block transfer operation. Direct Memory Access mode is enabled
via EMSR bits 2 and 3. The Direct Memory Access transaction is controlled through the RXDRQ [A-D],
TXDRQ [A-D], DACK [A-D], AEN and TC pins.
2.9
DMA Mode
The DMA Mode (a legacy term) in this document doesn’t mean “direct memory access” but refers to data block
transfer operation. (Since the 864 also supports Direct Memory Access, “Direct Memory Access” will be used
instead of “DMA” when explaining Direct Memory Access.) The DMA mode affects the state of the RXRDY# A-
D and TXRDY# A-D output pins. The transmit and receive FIFO trigger levels provide additional flexibility to the
user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is empty or has an
empty location(s) for more data. The user can optionally operate the transmit and receive FIFO in the DMA
mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is disabled (FCR
bit-3 = 0), the 864 is placed in single-character mode for data transmit or receive operation. When DMA mode
is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or unloading the FIFO
in a block sequence determined by the programmed trigger level. The following table show their behavior. Also
see Figure 19 through 23.
2.10
Crystal Oscillator or External Clock Input
The 864 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for all four UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see
“Programmable Baud Rate Generator.”
FIGURE 4. TYPICAL OSCILATOR CONNECTIONSL
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
TABLE 5: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE FOR CHANNELS A-D
PINS
FCR BIT-0=0
(FIFO DISABLED)
FCR BIT-0=1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
RXRDY#
0 = 1 byte
1 = no data
0 = at least 1 byte in FIFO
1 = FIFO empty
1 to 0 transition when FIFO reaches the trigger
level, or timeout occurs.
0 to 1 transition when FIFO empties.
TXRDY#
0 = THR empty
1 = byte in THR
0 = FIFO empty
1 = at least 1 byte in FIFO
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
C 1
2 2 -47 p F
C 2
2 2 -4 7 pF
1 4 .7 45 6
M H z
X T A L1
X T A L2
R = 30 0 K to 40 0 K
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