参数资料
型号: XR16L2551ILTR-F
厂商: Exar Corporation
文件页数: 14/49页
文件大小: 0K
描述: IC UART FIFO 16B DUAL 32QFN
标准包装: 3,000
特点: *
通道数: 2,DUART
FIFO's: 16 字节
规程: RS232,RS485
电源电压: 2.25 V ~ 5.5 V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN 裸露焊盘(5x5)
包装: 带卷 (TR)
XR16L2551
21
REV. 1.1.3
LOW VOLTAGE DUART WITH POWERSAVE
2.18
Internal Loopback
The L2551 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 13 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input pins must be held to a logic 1 during
loopback test else upon exiting the loopback test the UART may detect and report a false “break” signal. Also,
Auto RTS/CTS is not supported during internal loopback.
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B
TXA/TXB
RXA/RXB
Modem
/
G
e
n
e
ral
Purpos
e
Cont
rol
Logic
Inte
rn
a
lD
a
ta
Bus
L
ines
and
Co
ntrol
Signa
ls
RTSA#/RTSB#
MCR bit-4=1
VCC
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
CTSA#/CTSB#
DTRA#/DTRB#
DSRA#/DSRB#
RIA#/RIB#
CDA#/CDB#
OP1#
OP2#
RTS#
CTS#
DTR#
DSR#
RI#
CD#
VCC
OP2A#/OP2B#
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