参数资料
型号: XR16L2750CMTR-F
厂商: Exar Corporation
文件页数: 5/48页
文件大小: 0K
描述: IC UART FIFO 64B DUAL 48TQFP
标准包装: 1,500
特点: *
通道数: 2,DUART
FIFO's: 64 字节
规程: RS232,RS485
电源电压: 2.25 V ~ 5.5 V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 48-TQFP
供应商设备封装: 48-TQFP(7x7)
包装: 带卷 (TR)
xr
XR16L2750
REV. 1.2.1
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
13
2.12.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
NOTE: Table-B selected as Trigger Table for
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
Receive Data S hift
Register (R S R )
Receive
D ata B yte
and E rrors
RHR Interrupt (IS R bit-2)
Receive Data
H olding R egister
(RHR)
RXF IF O 1
16X or 8X C lock
(EM S R bit-7)
Receive Data Characters
D ata Bit
V alidation
Error
T ags in
LS R bits
4:2
Receive Data Shift
Register (RSR)
RXFIFO1
16X or 8X Clock
(EMSR bit-7)
Er
ro
rT
ag
s
(6
4-set
s)
E
rro
rT
ag
s
in
LSR
bits
4:2
64 bytes by 11-bit
wide
FIFO
Receive Data Characters
FIFO
Trigger=16
Example
:
- RX FIFO trigger level selected at 16
bytes
(See Note Below)
Data fills to
24
Data falls to
8
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
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