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参数资料
型号： XR16L788IQTR-F
厂商： Exar Corporation
文件页数： 1/54页
文件大小： 0K
描述： IC UART FIFO 64B OCTAL 100QFP
标准包装： 500
特点： *
通道数： 8
FIFO's： 64 字节
规程： RS485
电源电压： 2.97 V ~ 5.5 V
带自动流量控制功能： 是
带IrDA 编码器/解码器： 是
带故障启动位检测功能： 是
带调制解调器控制功能： 是
安装类型： 表面贴装
封装/外壳： 100-BQFP
供应商设备封装： 100-QFP（14x20）
包装： 带卷 (TR)
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XR16L788
HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART
JULY 2008
REV. 1.2.3
GENERAL DESCRIPTION
The XR16L7881 (788), is a 2.97V to 5.5V with 5V
tolerant
inputs
octal
Universal
Asynchronous
Receiver
and
Transmitter
(UART).
The
highly
integrated device is designed for high bandwidth
requirement in communication systems. The global
interrupt source register provides a complete interrupt
status indication for all 8 channels to speed up
interrupt parsing. Each UART has its own 16C550
compatible set of configuration registers, TX and RX
FIFOs of 64 bytes, fully programmable transmit and
receive FIFO trigger levels, TX and RX FIFO level
counters, automatic RTS/CTS or DTR/DSR hardware
flow control with programmable hysteresis, autoamtic
software (Xon/Xoff) flow control, RS-485 half-duplex
direction control with programmable turn-around
delay, Intel or Motorola bus interface and sleep mode
with a wake-up indicator.
NOTE: Covered by US patents #5,649,122 and #5,949,787
APPLICATIONS
Remote Access Servers
Ethernet Network to Serial Ports
Network Management
Factory Automation and Process Control
Point-of-Sale Systems
Multi-port RS-232/RS-422/RS-485 Cards
FEATURES
2.97V to 5.5V with 5V Tolerant Inputs Operation
Single Interrupt Output for all 8 UARTs
Global Interrupt Source for all 8 UARTs
5G “Flat” UART Registers for Configurations
Simultaneous UART Channels Initialization
Auto RS485 Half-duplex Control with Program-
mable Turn-around Delay
A General Purpose 16-bit Timer/Counter
Sleep Mode with Wake-up Indication
Highly Integrated Device for Space Saving
First eight registers are 16C550 compatible
64-byte Transmit and Receive FIFOs
Transmit and Receive FIFO Level Counters
Programmable TX and RX FIFO Trigger Levels
Automatic RTS/CTS or DTR/DSR Flow Control
Selectable Hardware Flow Control Hysteresis
Automatic Xon/Xoff Software Flow Control with
Status Indicator
Infrared (IrDA 1.0) Data Encoder/Decoder
Programmable Data Rate with Prescaler
Up to 6.25 Mbps Serial Data Rate at 5V
100-pin QFP Package (14x20x3 mm)
FIGURE 1. BLOCK DIAGRAM
TMRCK
Device
Configuration
Registers
XTAL1
XTAL2
Crystal Osc/Buffer
UART Channel 0
TX0, RX0, DTR0#,
DSR0#, RTS0#,
CTS0#, CD0#, RI0#
Data Bus
Interface
RST#
A7:A0
IOR#
IOW#
CS#
INT#
TX7, RX7, DTR7#,
DSR7#, RTS7#,
CTS7#, CD7#, RI7#
UART Channel 7
UART Channel 6
UART Channel 5
UART Channel 4
UART Channel 3
UART Channel 2
UART Channel 1
16-bit
Timer/Counter
64 Byte TX FIFO
64 Byte RX FIFO
BRG
IR
ENDEC
TX & RX
UART
Regs
D7:D0
16/68#
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