参数资料
型号: XR16M554IL-0A-EVB
厂商: Exar Corporation
文件页数: 13/46页
文件大小: 0K
描述: EVAL BOARD FOR XR16M554-A 48QFN
标准包装: 1
系列: *
XR16M554/554D
20
1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO
REV. 1.0.0
4.0
INTERNAL REGISTER DESCRIPTIONS
4.1
Receive Holding Register (RHR) - Read- Only
4.2
Transmit Holding Register (THR) - Write-Only
4.3
Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
TABLE 8: INTERNAL REGISTERS DESCRIPTION.
ADDRESS
A2-A0
REG
NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
16C550 Compatible Registers
0 0 0
RHR
RD
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7] = 0
0 0 0
THR
WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0 0 1
IER
RD/WR
0
Modem
Stat. Int.
Enable
RX Line
Stat.
Int.
Enable
TX
Empty
Int
Enable
RX
Data
Int.
Enable
0 1 0
ISR
RD
FIFOs
Enabled
FIFOs
Enabled
0
INT
Source
Bit-3
INT
Source
Bit-2
INT
Source
Bit-1
INT
Source
Bit-0
0 1 0
FCR
WR
RX FIFO
Trigger
RX FIFO
Trigger
0
DMA
Mode
Enable
TX
FIFO
Reset
RX
FIFO
Reset
FIFOs
Enable
0 1 1
LCR
RD/WR
Divisor
Enable
Set TX
Break
Set
Parity
Even
Parity
Enable
Stop
Bits
Word
Length
Bit-1
Word
Length
Bit-0
1 0 0
MCR
RD/WR
0
Internal
Lopback
Enable
INT
Output
Enable
(OP2#)
Rsvd
(OP1#)
RTS#
Output
Control
DTR#
Output
Control
LCR[7] = 0
1 0 1
LSR
RD/WR
RX
FIFO
Global
Error
THR &
TSR
Empty
THR
Empty
RX Break
RX
Framing
Error
RX
Parity
Error
RX
Over-
run
Error
RX
Data
Ready
1 1 0
MSR
RD/WR
CD#
Input
RI# Input
DSR#
Input
CTS#
Input
Delta
CD#
Delta
RI#
Delta
DSR#
Delta
CTS#
1 1 1
SPR
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Baud Rate Generator Divisor
0 0 0
DLL
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7]=1
LCR
≠0xBF
0 0 1
DLM
RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
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