参数资料
型号: XR16M570IB25-F
厂商: Exar Corporation
文件页数: 30/50页
文件大小: 0K
描述: IC UART FIFO 16B 25BGA
标准包装: 714
特点: *
通道数: 1,UART
FIFO's: 16 字节
规程: RS232,RS422,RS485
电源电压: 1.62 V ~ 3.63 V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 25-WFBGA
供应商设备封装: 25-BGA(3x3)
包装: 托盘
XR16M570
36
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
REV. 1.0.1
EMSR[2]: Send TX Immediately
Logic 0 = Do not send TX immediately (default).
Logic 1 = Send TX immediately. When FIFO is enabled and this bit is set, the next data will be to the TX shift
register. Thus, the data will be sent out immediately instead of queuing in the FIFO. Every time, only 1 byte
will be send out. Once this byte has been sent out, the EMSR[2] will go back to 0 automatically. If more than
1 byte will be sent out, EMSR[2] needs to be set to 1 for each byte.
EMSR[3]: Invert RTS in RS485 mode
Logic 0 = RTS# output is a logic 0 during TX and a logic 1 during RX (default).
Logic 1 = RTS# output is a logic 1 during TX and a logic 0 during RX.
EMSR[5:4]: Reserved
EMSR[6]: LSR Interrupt Mode
Logic 0 = LSR Interrupt Delayed (default). LSR bits 2, 3, and 4 will generate an interrupt when the character
with the error is in the RHR.
Logic 1 = LSR Interrupt Immediate. LSR bits 2, 3, and 4 will generate an interrupt as soon as the character is
received into the FIFO.
EMSR[7]: Xoff/Special character Interrupt Mode Select
This bit selects how the Xoff and Special character interrupt is cleared. The XON interrupt can only be cleared
by reading the ISR register.
Logic 0 = Xoff interrupt is cleared by either reading ISR register or when an XON character is received.
Special character interrupt is cleared by either reading ISR register or when next character is received.
(default).
Logic 1 = Xoff/Special character interrupt can only be cleared by reading the ISR register.
4.13
Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write
These registers make-up the value of the baud rate divisor. The M570 has different DLL, DLM and DLD for
transmitter and receiver. It provides more convenience for the transmitter and receiver to transmit data with
different rate. The M570 uses DLD[7:6] to select TX or RX. Then it provides DLD[5:0] to select the sampling
frequency and fractional baud rate divisor. The concatenation of the contents of DLM and DLL gives the 16-bit
divisor value. The value is added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be
enabled via EFR bit-4 before it can be accessed. See Table 13 below and See ”Section 2.7, Programmable
Baud Rate Generator with Fractional Divisor” on page 11.
DLD[5:4]: Sampling Rate Select
These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will
double if the 8X mode is selected and will quadruple if the 4X mode is selected. See Table 13 below.
TABLE 13: SAMPLING RATE SELECT
DLD[5]
DLD[4]
SAMPLING RATE
00
16X
01
8X
1X
4X
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