参数资料
型号: XR16V2750IMTR-F
厂商: Exar Corporation
文件页数: 13/52页
文件大小: 0K
描述: IC UART FIFO 64B DUAL 48TQFP
标准包装: 1,500
特点: *
通道数: 2,DUART
FIFO's: 64 字节
规程: RS232,RS485
电源电压: 2.25 V ~ 3.6 V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 48-TQFP
供应商设备封装: 48-TQFP(7x7)
包装: 带卷 (TR)
XR16V2750
20
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
REV. 1.0.3
2.20
Sleep Mode with Auto Wake-Up
The V2750 supports low voltage system designs, hence, a sleep mode is included to reduce its power
consumption when the chip is not actively used.
All of these conditions must be satisfied for the V2750 to enter sleep mode:
no interrupts pending for both channels of the V2750 (ISR bit-0 = 1)
sleep mode of both channels are enabled (IER bit-4 = 1)
modem inputs are not toggling (MSR bits 0-3 = 0)
RX input pins are idling HIGH
The V2750 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for
no clock output as an indication that the device has entered the sleep mode.
The V2750 resumes normal operation by any of the following:
a receive data start bit transition (HIGH to LOW)
a data byte is loaded to the transmitter, THR or FIFO
a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#
If the V2750 is awakened by any one of the above conditions, it will return to the sleep mode automatically after
all interrupting conditions have been serviced and cleared. If the V2750 is awakened by the modem inputs, a
read to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while
an interrupt is pending from channel A or B. The V2750 will stay in the sleep mode of operation until it is
disabled by setting IER bit-4 to a logic 0.
If the address lines, data bus lines, IOW#, IOR#, CSA#, CSB#, and modem input lines remain steady when the
V2750 is in sleep mode, the maximum current will be in the microamp range as specified in the DC Electrical
Characteristics on page 41. If the input lines are floating or are toggling while the V2750 is in sleep mode, the
current can be up to 100 times more. If any of those signals are toggling or floating, then an external buffer
would be required to keep the address, data and control lines steady to achieve the low current. As an
alternative, please refer to the XR16L2751 which is pin-to-pin and software compatible with the V2750 but with
(some additional pins and) the PowerSave feature that eliminates any unnecessary external buffer.
A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the
first few receive characters may be lost. The number of characters lost during the restart also depends on your
operating data rate. More characters are lost when operating at higher data rate. Also, it is important to keep
RX A/B inputs idling HIGH or “marking” condition during sleep mode to avoid receiving a “break” condition
upon the restart. This may occur when the external interface transceivers (RS-232, RS-485 or another type)
are also put to sleep mode and cannot maintain the “marking” condition. To avoid this, the designer can use a
47k-100k ohm pull-up resistor on the RXA and RXB pins.
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