参数资料
型号: XR16V564DIV-F
厂商: Exar Corporation
文件页数: 30/54页
文件大小: 0K
描述: IC UART FIFO 32B QUAD 64LQFP
标准包装: 160
特点: *
通道数: 4,QUART
FIFO's: 32 字节
规程: RS232
电源电压: 2.25 V ~ 3.6 V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
XR16V564/564D
36
2.25V TO 3.6V QUAD UART WITH 32-BYTE FIFO
REV. 1.0.4
4.11
Baud Rate Generator Registers (DLL and DLM) - Read/Write
These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and DLL
gives the 16-bit divisor value. Then the value is added to DLD[3:0]/16 to achieve the fractional baud rate
divisor. DLD must be enabled via EFR bit-4 before it can be accessed. See Table 15 below and See ”Section
DLD[5:4]: Sampling Rate Select
These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will
double if the 8X mode is selected and will quadruple if the 4X mode is selected. See Table 15 below.
TABLE 15: SAMPLING RATE SELECT
SAMPLING RATE
0
16X
0
1
8X
1
X
4X
DLD[7:6]: Reserved
4.12
Enhanced Feature Register (EFR) - Read/Write
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 16). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
DLD[5]
DLD[4]
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