参数资料
| 型号： | XR16V654IV-F |
| 厂商： | Exar Corporation |
| 文件页数： | 8/58页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 64B QUAD 64LQFP |
| 标准包装： | 160 |
| 特点： | * |
| 通道数： | 4，QUART |
| FIFO's： | 64 字节 |
| 规程： | RS232 |
| 电源电压： | 2.25 V ~ 3.6 V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
| 其它名称： | 1016-1469 XR16V654IV-F-ND |
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XR16V654/654D
16
2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO
REV. 1.0.1
the value of ’1’ (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon reset. Therefore, the BRG must be
programmed during initialization to the operating data rate. The DLL and DLM registers provide the integer part
of the divisor and the DLD register provides the fractional part of the divisor. Only the four lower bits of the DLD
are implemented and they are used to select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting
1111). Programming the Baud Rate Generator Registers DLL, DLM and DLD provides the capability for
selecting the operating data rate. Table 6 shows the standard data rates available with a 24MHz crystal or
external clock at 16X clock rate. If the pre-scaler is used (MCR bit-7 = 1), the output data rate will be 4 times
less than that shown in Table 6. At 8X sampling rate, these data rates would double. And at 4X sampling rate,
they would quadruple. Also, when using 8X sampling mode, please note that the bit-time will have a jitter (+/- 1/
16) whenever the DLD is non-zero and is an odd number. When using a non-standard data rate crystal or
external clock, the divisor value can be calculated with the following equation(s):
The closest divisor that is obtainable in the V654 can be calculated using the following formula:
In the formulas above, please note that:
TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.
ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.
A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 8 = 0x0078.
Required Divisor (decimal)=(XTAL1 clock frequency / prescaler) /(serial data rate x 16), with 16X mode, DLD[5:4]=’00’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 8), with 8X mode, DLD[5:4] = ’01’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 4), with 4X mode, DLD[5:4] = ’10’
ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where
DLM = TRUNC(Required Divisor) >> 8
DLL = TRUNC(Required Divisor) & 0xFF
DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)
FIGURE 7. BAUD RATE GENERATOR
XTAL1
XTAL2
Crystal
Osc/
Buffer
MCR Bit-7=0
(default)
MCR Bit-7=1
DLL, DLM and DLD
Registers
Prescaler
Divide by 1
Prescaler
Divide by 4
16X or 8X or 4X
Sampling
Rate Clock
to Transmitter
and Receiver
To Other
Channels
Fractional Baud
Rate Generator
Logic
相关PDF资料 |
PDF描述 |
|---|---|
| ST16C654CQ64-F | IC UART FIFO 64B QUAD 64LQFP |
| ST16C654DCQ64-F | IC UART FIFO 64B QUAD 64LQFP |
| ST16C654IQ100-F | IC UART FIFO 64B QUAD 100QFP |
| XR16V654IL-F | IC UART FIFO 64B QUAD 48QFN |
| XR16C2850CM-F | IC UART FIFO 128B DUAL 48TQFP |
相关代理商/技术参数 |
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| XR16V698IQ-0B-EVB | 功能描述:UART 接口集成电路 Supports V698 100 ld QFP, PCI Interface RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR16V698IQ100 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO |
| XR16V698IQ100-F | 功能描述:UART 接口集成电路 UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
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