参数资料
型号: XR17C154IV
厂商: Exar Corporation
文件页数: 62/62页
文件大小: 0K
描述: IC UART PCI BUS QUAD 144LQFP
产品变化通告: Leaded UART, V&I Obsolescence 11/Apr/2011
标准包装: 60
特点: *
通道数: 4,QUART
FIFO's: 64 字节
规程: RS485
电源电压: 5V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 144-LQFP
供应商设备封装: 144-LQFP(20x20)
包装: 托盘
xr
XR17C154
REV. 1.3.2
5V PCI BUS QUAD UART
9
1.2 DEVICE CONFIGURATION REGISTER SET
The device configuration registers and a special way to access each of the UART’s transmit and receive data
FIFOs are accessible directly from the PCI data bus. This provides easy programming of general operating pa-
rameters to the 154 UART and for monitoring the status of various functions. The registers occupy 2K of PCI
bus memory address space. These addresses are offset onto the basic memory address, a value loaded into
the Memory Base Address Register (BAR) in the PCI local bus configuration register set. These registers con-
trol or report on all 4 channel UARTs functions that include interrupt control and status, 16-bit general purpose
timer control and status, multipurpose inputs/outputs control and status, sleep mode control, soft-reset control,
and device identification and revision, and others.
The registers set is mapped into 4 address blocks where each UART channel occupies 512 bytes memory
space for its own 16550 compatible configuration registers. The device configuration and control registers are
embedded inside the UART channel zero’s address space between 0x0080 to 0x0093. All these registers can
be accessed in 8, 16, 24 or 32 bit width depending on the starting address given by the host at beginning of the
bus cycle. Transmit and receive data may be loaded or unloaded in 8, 16, 24 or 32 bit format to the register’s
address. Every time a read or write operation is made to the transmit or receive register, its FIFO data pointer
is automatically bumped to the next sequential data location either in byte, word or dword. One special case
applies to the receive data unloading when reading the receive data together with its LSR register content. The
host must read them in 16 or 32 bits format in order to maintain integrity of the data byte with its associated
error flags.
0x2C
31:16
RWR1
Subsystem ID (write from external EEPROM by customer)
0x0000
15:0
RWR1
Subsystem Vendor ID (write from external EEPROM by cus-
tomer)
0x0000
0x30
31:0
RO
Expansion ROM Base Address (Unimplemented)
0x00000000
0x34
31:0
RO
Reserved (returns zeros)
0x00000000
0x38
31:0
RO
Reserved (returns zeros)
0x00000000
0x3C
31:24
RO
Unimplemented MAXLAT
0x00
23:16
RO
Unimplemented MINGNT
0x00
15:8
RO
Interrupt Pin, use INTA#.
0x01
7:0
RWR
Interrupt Line.
0xXX
RWR1=Read/Write from external EEPROM. RWR=Read/Write from AD[31:0]. RO= Read Only. WO=Write Only.
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
ADDRESS
BITS
TYPE
DESCRIPTION
RESET VALUE
(HEX)
相关PDF资料
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