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参数资料
| 型号： | XR17V354IB-E4-EVB |
| 厂商： | Exar Corporation |
| 文件页数： | 50/66页 |
| 文件大小： | 0K |
| 描述： | EVAL BRD FOR XR17V354-E4 176BGA |
| 产品培训模块： | PCIe UARTs |
| 标准包装： | 1 |
| 主要目的： | 接口，UART |
| 嵌入式： | 否 |
| 已用 IC / 零件： | XR17V354 |
| 已供物品： | 板 |
| 其它名称： | 1016-1612 XR17V354IB-E4-EVB-ND |
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XR17V354
54
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
REV. 1.0.3
MCR[2]: DTR# or RTS# for Auto Flow Control (OP1 in Local Loopback Mode)
DTR# or RTS# auto hardware flow control select. This bit is in effect only when auto RTS/DTR is enabled by
EFR bit [6]. DTR# selection is associated with DSR# and RTS# is with CTS#.
Logic 0 = Uses RTS# and CTS# pins for auto hardware flow control.
Logic 1 = Uses DTR# and DSR# pins for auto hardware flow control.
In Local Loopback mode (MCR[4] = 1), this bit acts as the legacy OP1 output and controls the RI bit in the MSR
register, as shown in Figure 12.
MCR[1]: RTS# Output
The RTS# pin may be used for automatic hardware flow control by enabled by EFR bit [6] and MCR bit [2]=0. If
the modem interface is not used, this output may be used for general purpose.
Logic 0 = Force RTS# output to a HIGH (default).
Logic 1= Force RTS# output to LOW.
MCR[0]: DTR# Output
The DTR# pin may be used for automatic hardware flow control enabled by EFR bit [6] and MCR bit [2]=1. If
the modem interface is not used, this output may be used for general purpose.
Logic 0 = Force DTR# output to a HIGH (default).
Logic 1 = Force DTR# output to a LOW.
4.9
Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host. If IER bit [2] is set to a
logic 1, an LSR interrupt will be generated immediately when any character in the RX FIFO has an error (parity,
framing, overrun, break).
LSR[7]: Receive FIFO Data Error Flag
Logic 0 = No FIFO error (default).
Logic 1 = An indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error or
break indication is in the FIFO data. This bit clears when there are no more errors in the FIFO.
LSR[6]: Transmitter Empty Flag
This bit is the Transmitter Empty indicator. This bit is set to a logic 1 whenever both the transmit FIFO (or THR,
in non-FIFO mode) and the transmit shift register (TSR) are both empty. It is set to logic 0 whenever either the
TX FIFO or TSR contains a data character.
LSR[5]: Transmit FIFO Empty Flag
This bit is the Transmit FIFO Empty indicator. This bit indicates that the transmitter is ready to accept a new
character for transmission. This bit is set to a logic HIGH when the last data byte is transferred from the
transmit FIFO to the transmit shift register. The bit is reset to logic 0 as soon as a data byte is loaded into the
transmit FIFO. In the non-FIFO mode this bit is set when the transmit holding register (THR) is empty; it is
cleared when at a byte is written to the THR.
LSR[4]: Receive Break Flag
Logic 0 = No break condition (default).
Logic 1 = The receiver received a break signal (RX was LOW for one character frame time). In the FIFO
mode, only one break character is loaded into the FIFO. The break indication remains until the RX input
returns to the idle condition, “mark” or HIGH.
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相关代理商/技术参数 |
参数描述 |
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| XR17V354IB-E8-EVB | 功能描述:界面开发工具 Eval Board for XR17V354IB-E8 RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| XR17V358 | 制造商:EXAR 制造商全称:EXAR 功能描述:HIGH PERFORMANCE OCTAL PCI EXPRESS UART |
| XR17V358IB-0A-EVB | 功能描述:界面开发工具 Eval Board for XR17V358IB-0A RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| XR17V358IB176-F | 功能描述:UART 接口集成电路 8 Channel PCIe UART w/256 Byte FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR17V358IB176-F | 制造商:Exar Corporation 功能描述:IC OCTAL UART 25MBPS 3.6V 176-BGA |
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