
XR17V358
12
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
REV. 1.0.4
0x14
31:0
RWR
Unimplemented Base Address Register (returns zeros)
0x00000000
0x18h
31:0
RO
Unimplemented Base Address Register (returns zeros)
0x00000000
0x1C
31:0
RO
Unimplemented Base Address Register (returns zeros)
0x00000000
0x20
31:0
RO
Unimplemented Base Address Register (returns zeros)
0x00000000
0x24
31:0
RO
Unimplemented Base Address Register (returns zeros)
0x00000000
0x28
31:0
RO
Reserved
0x00000000
0x2C
31:16
EWR
Subsystem ID (write from external EEPROM by customer)
0x0000
15:0
EWR
Subsystem Vendor ID (write from external EEPROM by cus-
tomer)
0x0000
0x30
31:0
RO
Expansion ROM Base Address (Unimplemented)
0x00000000
0x34
31:8
RO
Reserved (returns zeros)
0x000000
7:0
RO
Capability Pointer
0x50
0x38
31:0
RO
Reserved (returns zeros)
0x00000000
0x3C
31:24
RO
Unimplemented MAXLAT
0x00
23:16
RO
Unimplemented MINGNT
0x00
15:8
RO
Interrupt Pin, use INTA#.
0x01
7:0
RWR
Interrupt Line.
0xXX
0x40
31:0
RO
Not implemented or not applicable (return zeros)
0x00000000
0x44
31:0
RO
CSR
0x02106160
0x48
31:0
RO
Not implemented or not applicable (return zeros)
0x00000000
0x4C
31:0
RO
Not implemented or not applicable (return zeros)
0x00000000
0x50
31:16
RO
64-bit address capable
0x0080
15:8
RO
Next Capability Pointer
0x78
7:0
RO
MSI Capable Capability ID
0x05
0x54-0x67 31:0
RO
Not implemented or not applicable (return zeros)
0x00000000
0x68
31:0
RO
Not implemented or not applicable
0x0000xxxx
0x6C-0x77 31:0
RO
Not implemented or not applicable (return zeros)
0x00000000
0x78
31:16
RO
PME# support (PME# can be asserted from D3hot and D0)
PCI Power Management 1.2
0x4803
15:8
RO
Next Capability Pointer
0x80
7:0
RO
Power Management Capability ID
0x01
0x7C
31:0
RO
No soft reset when transitioning from D3hot to D0 state
0x00000008
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
ADDRESS
OFFSET
BITS
TYPE
DESCRIPTION
RESET VALUE
(HEX OR BINARY)