参数资料
型号: XR19L200IL32-F
厂商: Exar Corporation
文件页数: 14/40页
文件大小: 0K
描述: IC UART/TXRX RS232 32QFN
标准包装: 490
特点: *
通道数: 1,UART
FIFO's: 16 字节
规程: RS232
电源电压: 3 V ~ 5.5 V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN 裸露焊盘(5x5)
包装: 托盘
XR19L200
21
REV. 1.0.2
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
FCR[7:6]: Receive FIFO Trigger Select
(’00’ = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 8 shows the selections.
4.7
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 9 for parity selection summary below.
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
TABLE 8: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION
FCR
BIT-7
FCR
BIT-6
FCR
BIT-5
FCR
BIT
-4
RECEIVE
TRIGGER LEVEL
TRANSMIT
TRIGGER LEVEL
COMPATIBILITY
0
1
0
1
0
1
1 (default)
4
8
14
16L580 and 16C580 compatible.
0
1
0
1
0
1
1 (default)
4
8
14
16L580, 16C550, 16C580, 16C554,
16C2550 and 16C2552 compatible
BIT-1
BIT-0
WORD LENGTH
0
5 (default)
0
1
6
1
0
7
1
8
BIT-2
WORD
LENGTH
STOP BIT LENGTH
(BIT TIME(S))
0
5,6,7,8
1 (default)
1
5
1-1/2
1
6,7,8
2
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