参数资料
| 型号： | XR19L222IL64-F |
| 厂商： | Exar Corporation |
| 文件页数： | 21/53页 |
| 文件大小： | 0K |
| 描述： | IC UART/TXRX RS232 64QFN |
| 标准包装： | 260 |
| 特点： | * |
| 通道数： | 2，DUART |
| FIFO's： | 64 字节 |
| 规程： | RS232 |
| 电源电压： | 3.3 V ~ 5.5 V |
| 带自动流量控制功能： | 是 |
| 带IrDA 编码器/解码器： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘 |
| 供应商设备封装： | 64-QFN（9x9） |
| 包装： | 托盘 |
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XR19L222
28
TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
4.4.2
Interrupt Clearing:
LSR interrupt is cleared by a read to the LSR register.
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
MSR interrupt is cleared by a read to the MSR register.
Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received.
Special character interrupt is cleared by a read to ISR or after the next character is received.
RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
Wake-up Indicator is cleared by a read to the ISR register.
]
ISR[0]: Interrupt Status
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition) or the device has come out of sleep mode.
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 9).
ISR[4]: Xoff or Special Character Interrupt Status (requires EFR bit-4=1)
This bit is enabled when IER[5] = 1. ISR bit-4 indicates that the receiver detected a data match of the Xoff
character(s) or special character (XOFF2).
ISR[5]: RTS#/CTS# Interrupt Status (requires EFR bit-4=1)
This bit is enabled when IER[7] = 1 or IER[6] = 1. ISR bit-5 indicates that the CTS# or RTS# has been de-
asserted.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF INTERRUPT
LEVEL
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
1
0
1
0
LSR (Receiver Line Status Register)
2
0
1
0
RXRDY (Receive Data Time-out)
3
0
1
0
RXRDY (Received Data Ready)
4
0
1
0
TXRDY (Transmit Ready)
5
0
MSR (Modem Status Register)
6
0
1
0
RXRDY (Received Xoff or Special character)
7
1
0
CTS#, RTS# change of state
-
0
1
None (default) or Wake-up Indicator
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