参数资料
型号: XR21V1412IL32-F
厂商: Exar Corporation
文件页数: 2/32页
文件大小: 0K
描述: IC UART FIFO USB DUAL 32QFN
产品培训模块: UART Product Overview
XR21V141x Full-Speed USB UART Family
特色产品: XR21V141x Full-Speed USB UART
标准包装: 490
特点: *
通道数: 2,DUART
FIFO's: 128 字节,384 字节
规程: USB 2.0
电源电压: 2.97 V ~ 3.63 V
带自动流量控制功能:
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN 裸露焊盘(5x5)
包装: 托盘
配用: 1016-1301-ND - EVAL BOARD FOR XR21V1412IL
其它名称: 1016-1302
XR21V1412
10
2-CH FULL-SPEED USB UART
REV. 1.3.0
FIGURE 3. NORMAL OPERATION RECEIVE DATA FORMAT
1.5.2.3
Wide mode receive operation with 7 or 8-bit data
Two bytes of data are loaded into the RX FIFO for each byte of data received. The first byte is the received
data. The second byte consists of the error bits and break status. Wide mode receive data format is shown in
Figure 4.
1.5.2.4
Wide mode receive operation with 9-bit data
Two bytes of data are loaded into the RX FIFO for each byte of data received. The first byte is the first 8 bits of
the received data. The 9th bit received is stored in the bit 0 of the second byte. The parity bit is not received /
checked. The remainder of the 2nd byte consists of the framing and overrun error bits and break status.
FIGURE 4. WIDE MODE RECEIVE DATA FORMAT
Error flags are also available from the ERROR_STATUS register and the interrupt packet, however these flags
are historical flags indicating that an error has occurred since the previous request. Therefore, no conclusion
can be drawn as to which specific byte(s) may have contained an actual error in this manner.
1.5.3
Rx FIFO Low Latency
In normal operation all bulk-in transfers will be of maxPacketSize (64) bytes to improve throughput and to
minimize host processing. When there are 64 bytes of data in the RX FIFO, the V1412 will acknowledge a
bulk-in request from the host and transfer the data packet. If there is less than 64 bytes in the RX FIFO, the
V1412 may NAK the bulk-in request indicating that data is not ready to transfer at that time. However, if there
is less than 64 bytes in the RX FIFO and no data has been received for more than 3 character times, the
V1412 will acknowledge the bulk-in request and transfer any data in the RX FIFO to the USB host.
In some cases, especially when the baud rate is low, this increases latency unacceptably. The V1412 has a
low latency register bit that will cause the V1412 to immediately transfer any received data in the RX FIFO to
the USB host, i.e. it will not wait for 3 character times.
The custom driver can automatically set the
1
ST byte
7, 8, or 9bit data
7 6 5 4 3 2 1 0
7=‘0’ in7bit mode
1st byte
2nd byte
9 bit mode
7
6
5
4
3
2
1
0
x
O F B P
1st byte
B = Break
F = Framing Error
O = Overrun Error
2nd byte
7 or 8 bit mode
P = Parity Error (= ‘0’ if not enabled)
7 = ‘0’ in 7 bit mode
x = ‘0’
7
6
5
4
3
2
1
0
x
O F B 8
B = Break
F = Framing Error
O = Overrun Error
x = ‘0’
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