
XR-2211A
16
Rev. 1.04
Design Instructions:
The circuit of
Figure 12 can be optimized for any tone detection application by the choice of the 5 key circuit components:
R0, R1, C0, C1 and CD. For a given input, the tone frequency, fS, these parameters are calculated as follows:
(All resistance in
W’s, all frequency in Hz and all capacitance in farads, unless otherwise specified)
a) Choose value of timing resistor R0 to be in the range of 10KW to 50KW. This choice is dictated by the max./min.
current that the internal voltage reference can deliver. The recommended value is R0 = 20KW. The final value of R0
is normally fine-tuned with the series potentiometer, RX.
b) Calculate value of C0 from design equation (1) or from Figure 7 fS = fO:
C
O +
1
R
0fs
c)
Calculate R1 to set the bandwidth +Df (See design equation 5):
R
1
+
R
0f02
Df
Note: The total detection bandwidth covers the frequency range of fO +Df
d) Calculate value of C1 for a given loop damping factor:
Normally,
j = 0.5 is recommended.
C
1
+
1250
C
0
R
1
j2
Increasing C1 improves the out-of-band signal rejection, but increases the PLL capture time.
e) Calculate value of the filter capacitor CD . To avoid chatter at the logic output, with RD = 470KW, CD must be:
C
D
§ 16
Df
Cin
mF
Increasing CD slows down the logic output response time.
Design Examples:
Tone detector with a detection band of + 100Hz:
a) Choose value of timing resistor R0 to be in the range of 10KW to 50KW. This choice is dictated by the max./min.
current that the internal voltage reference can deliver. The recommended value is R0 = 20 KW. The final value of R0
is normally fine-tuned with the series potentiometer, RX.
b) Calculate value of C0 from design equation (1) or from Figure 6 fS = fO:
C
0
+ 1
R
0fS
+
1
20, 0001, 000
+ 50nF