- 您现在的位置：买卖IC网 > PDF目录16522 > XR68M752IM-0B-EB (Exar Corporation)EVAL BOARD FOR XR68M752 48TQFP PDF资料下载
参数资料
| 型号： | XR68M752IM-0B-EB |
| 厂商： | Exar Corporation |
| 文件页数： | 9/54页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XR68M752 48TQFP |
| 标准包装： | 1 |
| 系列： | * |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页
XR16M752/XR68M752
17
REV. 1.1.1
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
2.10
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X/4X clock (DLD [5:4]) for timing. It
verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of
a start or false start bit, an internal receiver counter starts counting at the 16X/8X/4X clock rate. After 8 clocks
(or 4 if 8X or 2 if 4X) the start bit period should be at the center of the start bit. At this time the start bit is
sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same
manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon
unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are
immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data
ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data
delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4
word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR
interrupt is enabled by IER bit-0.
2.10.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE
R eceive D ata Shift
R egister (R SR)
Receive
D ata Byte
and Errors
R H R Interrupt (ISR bit-2)
Receive Data
H olding R egister
(R H R)
R XFIFO 1
16X or 8X or 4X C lock
( D LD[5:4] )
R eceive Data Characters
D ata Bit
Validation
Error
Tags in
LSR bits
4:2
相关PDF资料 |
PDF描述 |
|---|---|
| VI-J04-EZ-S | CONVERTER MOD DC/DC 48V 25W |
| H3CKH-5018G | IDC CABLE - HKC50H/AE50G/HPK50H |
| EBM28DTAH-S189 | CONN EDGECARD 56POS R/A .156 SLD |
| XR68M752IL-0B-EB | EVAL BOARD FOR XR68M752 32QFN |
| LBR2518T101M | INDUCTOR WOUND 100UH 80MA 1007 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XR68M752IM48 | 制造商:EXAR 制造商全称:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 64-BYTE FIFO |
| XR68M752IM48-F | 功能描述:UART 接口集成电路 UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR68M752IM48TR-F | 制造商:Exar Corporation 功能描述:XR68M752 Series 16 Mbps High Performance DUART With 64-Byte FIFO - TQFP-48 |
| XR7090AA-BC-0001 | 制造商:CREE 制造商全称:Cree, Inc 功能描述:XLamp㈢ XR LED Binning and Labeling |
| XR7090AA-BC-DD-EF-G-HHHH | 制造商:CREE 制造商全称:Cree, Inc 功能描述:XLamp㈢ XR LED Binning and Labeling |
发布紧急采购，3分钟左右您将得到回复。