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参数资料
型号： XR82C684J-F
厂商： Exar Corporation
文件页数： 23/107页
文件大小： 0K
描述： IC UART CMOS QUAD 68PLCC
标准包装： 19
特点： *
通道数： 4，QUART
FIFO's： 3 字节
电源电压： 5V
安装类型： 表面贴装
封装/外壳： 68-LCC（J 形引线）
供应商设备封装： 68-PLCC
包装： 管件
XR82C684
6(, * " '' $* '' (%
3((, ( '% ;) (% * # (% ( 3( %
,( * ( # 3 '' (%
( ;)
Note:
If this bit is configured to reflect the FFULLB
indicator, this bit will not be set (nor will produce an
interrupt request) if one or two characters are still
remaining in RHRB, following data reception. Hence, it is
possible that the last two characters in a string of data
(being received) could be lost due to this phenomenon.
ISR1[4] TXRDYB - Channel B Transmitter Ready
(% ( (% (' * 8!H )# )PQ
(% (# 3 %# (('% ;) (% & (%
& '' '' * + ( (%
' 3 + 3(% 3 '' ;).
(% % ,(# 3 '' (% %*
8!H) (% % 3 %( (% ((( &
(% ' 3 %( (% (%
'% ( ;) 3( %( (%
(% 3( %(
ISR1[3] Counter #1 Ready
$ $5 # - D -( D 3( %
$P4Q ' * ' '&' * % %I 3
3(' (% ( +4 ( $P4Q 3( '
& ( 6(, %%(,, /+ :5 1
' ) ( (# ( $5 #
/+ :51 ' 3( % -
$ :5 # (% ( (% % 3 ' D
'% ( ' (% ' 3
' (% % & /+ :51
' E -( (% ( :5
# /+ :51 ' 3( %
-( ( (%'%%( ( *
-(% ' * ( Section D
ISR1[2]: Delta Break A - Channel A Change in
Break
%%( * (% ( (('% ' '(
% ' ,((, * * '(
6 ) (% ( (% ' 3 + ( 6%
' /55 )5= ;:25 $:5+1
' (* ( ( K%
% % )5= ' (( # % % Section G.2
ISR1[1] RXRDYA/FFULL A - Channel A Receiver
Ready or FIFO Full
*'( * (% ( (% % ' & ,(,
P.Q $* (% ( *( (% ' *(, *'( %
/'( &1 ((' 8!H# /1 ( (% (
*( (('% (% % '' * (
;# (% & & + (% ( (% %
3 '' (% %* * ;
(% ' 3 + % / %1 ; $*
%( ''% ( ;# * 3(,
( # ( 3( % ,( * ; (%
/ 1
$* (% ( (% ' *(, *'( % $ ; *
((' <<# ( (% % 3 '' (%
%* * ; 3 &
%* '' '%% ; ' * (%
( (% ' 3 + % ; $* '' (%
3((, ( '% ; (% * # (% ( 3( %
,(# * 3(, ( # 3 '' (%
( ;
Note:
If this bit is configured to reflect the FFULLA
indicator, this bit will not be set (nor will produce an
interrupt request) if one or two characters are still
remaining in RHRA, following data reception. Hence, it is
possible that the last two characters in a string of data
(being received) could be lost due to this phenomenon.
Therefore, the user is advised to read RHRA until empty.
ISR1[0]: Channel A Transmitter Ready
(% ( (% (' * 8!H # PQ
(% (# 3 %# (('% ; (% & (%
& '' '' * + ( (%
' 3 + 3(% 3 '' ;.
(% % ,(# 3 '' (% %*
8!H (% % 3 %( (% ((( &
(% ' 3 %( (% (%
'% ( ; 3( %( (%
(% 3( %(
C.1.2 ISR2 Register - Channels C and D
ISR2[7]: Input Port Change of State:
$* (% ( (% ,(' /1# ', * % 3%
' $ + (% $+0 $+ % %('%
(% ( & (, $+ (* $PBQ L
$PBQ (% ' 3 + % $ +
*(,( ,(% $+ )& (, $+#
% 3( (7
((( $ + ( ', %
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