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参数资料
| 型号： | XR88C681P/40 |
| 厂商： | Exar Corporation |
| 文件页数： | 18/101页 |
| 文件大小： | 0K |
| 描述： | IC UART CMOS DUAL 40PDIP |
| 产品变化通告： | Leaded UART, V&I Obsolescence 11/Apr/2011 |
| 标准包装： | 9 |
| 特点： | * |
| 通道数： | 2，DUART |
| FIFO's： | 1 字节，3 字节 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 带并行端口： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 通孔 |
| 封装/外壳： | 40-DIP（0.600"，15.24mm） |
| 供应商设备封装： | 40-PDIP |
| 包装： | 管件 |
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XR88C681
23
Rev. 2.11
program control to a specific location in system memory.
For CPUs that employ direct interrupts, this “location” is
fixed by the CPU circuitry itself.
For Example:
If the -INT0 interrupt request input pin, of the 8051 C, is
asserted, the CPU will branch program control to location
000316 in system memory. This location is fixed (by circuit
design of the 8051 P) and cannot be changed by the
user.
(External) Vectored Interrupt Processing
CPUs that employ this form of interrupt processing
typically have an Interrupt Acknowledge output pin. This
“IACK” or “-INTA” output will be used to gate “interrupt
vector” information onto the Data Bus, via external
(non-DUART) hardware. The term “External” is used to
describe this form of vectored-interrupt processing;
because the location of the interrupt service routine is
determined by hardware “external” to the DUART. For
some CPUs, (such as the 8080A and the 8085 P), this
“interrupt vector” information is a one byte op-code for a
CALL instruction to a special “RESTART subroutine”.
The location of this “RESTART subroutine” is fixed by
CPU circuit design. If the user employs this approach for
interrupt processing, he/she is responsible for insuring
that either the interrupt service routine, or an
unconditional branch instruction (to the interrupt service
routine) resides at this location in memory.
Each of these Interrupt Processing techniques will be
presented in greater detail in the following sections.
As mentioned earlier, the DUART should be operating in
the I-Mode, when interfaced to the P/ C presented in
Table 7. Table 7 also presents the type of interrupt
processing that is employed by each of these Ps/ Cs.
P/ C
Type of Interrupt Processing
Comments
8051 C
Direct
The 8051 C has two external Interrupt Request inputs: -INT0
and -INT1.
8080A P
External Vectored
The 8080A P will allow the use of up to 8 different op codes
for
“CALL” instructions to the Interrupt Service Routines.
The 8080A CPU module will output an interrupt ac-
knowledge output, -INTA, which can be used to “gate”
the “CALL” instructions on to the Data Bus.
8085 P
Direct and External Vectored
The 8085 P has three “Direct” external Interrupt Request
inputs: RST 7.5, RST 6.5, and RST 5.5. Additionally, this P
has the exact same “vector” options as does the 8080A P.
68HC11 C
Direct
The 68HC11 C has a single “maskable” external Interrupt
Request input; -IRQ.
Z-80 P
(Interrupt Mode 0)
External Vectored
The Z-80 CPU uses the exact same approach as presented
for the 8080A CPU.
Z-80 P
Direct Interrupt
The Z-80 will branch to 0038H in system memory if the -INT
interrupt request pin is asserted.
Table 7. Summary of P/ C and their types of Interrupt Processing (I - Mode)
The information presented in
Table 7 is discussed in detail in the following sections.
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