参数资料
型号: XRA1201IL24-F
厂商: Exar Corporation
文件页数: 17/17页
文件大小: 0K
描述: IC I/O EXPANDER I2C 16B 24QFN
标准包装: 490
接口: I²C,SM 总线
输入/输出数: 16
中断输出:
频率 - 时钟: 400kHz
电源电压: 1.65 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-VFQFN 裸露焊盘
供应商设备封装: 24-QFN(4x4)
包装: 托盘
其它名称: 1016-1710
XRA1201/1201P
9
REV. 1.0.0
16-BIT I2C/SMBUS GPIO EXPANDER
2.9
Input Internal Pull-up Enable/Disable Register 1 (PUR1) - Read/Write
This register enables/disables the internal pull-up resistors for an input. After power-up and reset, the internal
pull-up resistors are disabled for the XRA1201. Writing a ’1’ to these bits will enable the internal pull-up
resistors. After power-up and reset, the internal pull-up resistors are enabled for the XRA1201P. Writing a ’0’
to these bits will disable the internal pull-up resistors. The MSB of this register corresponds with P7 and the
LSB of this register corresponds with P0.
2.10
Input Internal Pull-up Enable/Disable Register 2 (PUR2) - Read/Write
This register enables/disables the internal pull-up resistors for an input. After power-up and reset, the internal
pull-up resistors are disabled for the XRA1201. Writing a ’1’ to these bits will enable the internal pull-up
resistors. After power-up and reset, the internal pull-up resistors are enabled for the XRA1201P. Writing a ’0’
to these bits will disable the internal pull-up resistors. The MSB of this register corresponds with P15 and the
LSB of this register corresponds with P8.
2.11
Input Interrupt Enable Register 1 (IER1) - Read/Write
This register enables/disables the interrupts for an input. After power-up and reset, the interrupts are disabled.
Writing a ’1’ to these bits will enable the interrupt for the corresponding input pins. See Table 3 for complete
details of the interrupt behavior for various register settings. No interrupts are generated for outputs when GCR
bit is 0. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0.
2.12
Input Interrupt Enable Register 2 (IER2) - Read/Write
This register enables/disables the interrupts for an input. After power-up and reset, the interrupts are disabled.
Writing a ’1’ to these bits will enable the interrupt for the corresponding input pins. See Table 3 for complete
details of the interrupt behavior for various register settings. No interrupts are generated for outputs when GCR
bit is 0. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8.
2.13
Output Three-State Control Register 1 (TSCR1) - Read/Write
This register can enable/disable the three-state mode of an output. Writing a ’1’ to these bits will enable the
three-state mode for the corresponding output pins. The MSB of this register corresponds with P7 and the LSB
of this register corresponds with P0.
2.14
Output Three-State Control Register 2 (TSCR2) - Read/Write
This register can enable/disable the three-state mode of an output. Writing a ’1’ to these bits will enable the
three-state mode for the corresponding output pins. The MSB of this register corresponds with P15 and the
LSB of this register corresponds with P8.
2.15
Input Interrupt Status Register 1 (ISR1) - Read-Only
This register reports the input pins that have generated an interrupt. See Table 3 for complete details of the
interrupt behavior for various register settings. The MSB of this register corresponds with P7 and the LSB of
this register corresponds with P0.
2.16
Input Interrupt Status Register 2 (ISR2) - Read-Only
This register reports the input pins that have generated an interrupt. See Table 3 for complete details of the
interrupt behavior for various register settings. The MSB of this register corresponds with P15 and the LSB of
this register corresponds with P8.
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