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| 型号： | XRD98L61ZEVAL |
| 厂商： | Exar Corporation |
| 文件页数： | 11/38页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XRD98L61AIV |
| 标准包装： | 1 |
| 系列： | * |
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19
Rev. 2.00
XRD98L61
DIRECT PGA INPUT MODE
The inputs to the PGA can be accessed directly
(bypassing the CDS) through the Test1 & Test2 pins
(See Figure 1). The test inputs require Test2 set to a
dc voltage of 1.2V and the Test1 input signal between
1.2V and 0.4V. ADC Zero Scale (000h) is at 1.2V input
and Full Scale (FFFh)for a 0.4V input assuming a gain
of 8dB. (ADC full scale input is 2Vpp.)
To enable the Direct PGA Input mode, write a “1” to the
NoCDS bit in the Control register of the serial interface.
This will disconnect the CDS from the PGA input and
turn on the switches that connect the Test1 & Test2
pins to the PGA. Note that when the part is not in the
NoCDS mode that Test1 and Test2 are grounded
through an equivalent 10kohm switch resistance. To
avoid shorting the input drive circuitry into Test1 and
Test2 to ground, the NoCDS mode must be active
before the input signal is driven.
In this mode, the SBLK and SPIX clocks must be
clocked, due to the switched capacitor architecture of
the second PGA stage. ADCLK must be provided to
digitize the PGA output. The analog PGA output
cannot be monitored; it does not come out to any pin.
The calibration logic should be put into the Hold mode,
or into the ManCAL mode. The Coarse offset correction
DAC (CDAC) is disconnected from the PGA inputs in
this mode. The CDAC does not affect the Direct PGA
inputs, but the Fine offset correction DAC (FDAC) does
affect the PGA output. The FDAC range is +-128mV
at the ADC input. FDAC can be used to adjust offset
in the system when in the ManCal mode.
Note the calibration logic should not be in the automatic
mode, because the FDAC circuitry is not “aware” that
the Coarse DAC is not active, and thus could cause
errors if left operating automatically. Therefore, it is
recommended that either CAL Hold or Manual CAL
mode be asserted.
The DNL in the Direct PGA Input Mode is shown in
Figure 26.
Figure 8. Direct PGA Input Timing (Default Polarities)
Input Signal
Test1
PGA tracks
Input Signal
Input Sampled (N)
Input Sampled
(N+1)
ADC tracks
PGA output
SPIX
ADCLK
SBLK
DB[11:0]
nonoverlap=4ns
(N-8)
(N-7)
(N-6)
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