参数资料
型号: XRP6124ES0.5-F
厂商: Exar Corporation
文件页数: 8/12页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM SOT23-5
标准包装: 250
PWM 型: 控制器
输出数: 1
频率 - 最大: 833kHz
占空比: 92%
电源电压: 3 V ~ 18 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: SC-74A,SOT-753
包装: 散装
其它名称: 1016-1429
X R P 6 1 2 4
N o n - S y n c h r o n o u s P F E T S t e p - D o w n C o n t r o l l e r
R 1 = R 2 × ? OUT ? 1 ?
finished. If the feedback voltage drops below
0.55V, equivalent to output voltage dropping
below 69% of nominal, the comparator will
trip causing the IC to latch off. In order to
restart the XRP6124, the input voltage has to
be reduced below UVLO threshold and then
increased to its normal operating point.
SOFT - START
To limit in-rush current the XRP6124 has an
internal soft-start. The nominal soft-start time
is 2ms and commences when V IN exceeds the
UVLO threshold. As explained above, the
short-circuit comparator is enabled as soon as
soft-start is complete. Therefore if the input
voltage has a very slow rising edge such that
at the end of soft-start the output voltage has
not reached 69% of its final value then the
XRP6124 will latch-off.
ENABLE
By applying a logic-level signal to the enable
pin EN the XRP6124 can be turned on and off.
Pulling the enable below 1V shuts down the
controller and reduces the V IN leakage current
to 1.5μA nominal as seen in figure 18. Enable
signal should always be applied after the input
voltage or concurrent with it. Otherwise
APPLICATION INFORMATION
SETTING THE OUTPUT VOLTAGE
Use an external resistor divider to set the
output voltage. Program the output voltage
from:
? V ?
? 0 . 8 ?
XRP6124 will latch up. In applications where
an independent enable signal is not available,
a Zener diode can be used to derive V EN from
V IN .
DISCONTINUOUS CONDUCTION MODE , DCM
Because XRP6124 is a non-synchronous
controller, when load current I OUT is reduced to
less than half of peak-to-peak inductor current
ripple Δ IL, the converter enters DCM mode of
operation. The switching frequency fs is now
I OUT dependent and no longer governed by the
relationship shown in table 2. As I OUT is
decreased so does fs until a minimum
switching frequency, typically in the range of
few hundred Hertz, is reached at no load. This
contributes to good converter efficiency at
light load as seen in figures 4 and 5. The
reduced fs corresponding to light load,
however, increases the output voltage ripple
and causes a slight increase in output voltage
as seen in figures 8 and 9. Another effect of
reduced fs at light load is slow down of
transient response when a load step
transitions from a high load to a light load.
This is shown in figures 16 and 17.
FEED - FORWARD CAPACITOR CFF
CFF, which is placed in parallel with R1,
provides a low-impedance/high-frequency
path for the output voltage ripple to be
transmitted to FB. It also helps get an
optimum transient response. An initial value
for CFF can be calculated from:
where:
R1 is the resistor between V OUT and FB
CFF =
1
2 × π × fs × 0 . 1 × R 1
R2 is the resistor between FB and GND
(nominally 2k ? )
0.8V is the nominal feedback voltage.
where:
fs is the switching frequency from table 2
This value can be adjusted as necessary to
provide an optimum load step transient
response.
? 2011 Exar Corporation
8/12
Rev. 1.1.0
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