参数资料
型号: XRP6336ISCXDATR-F
厂商: Exar Corporation
文件页数: 5/10页
文件大小: 0K
描述: IC SUPERVISOR WATCHDOG 8TSOT
产品变化通告: SP6336 Number Change 5/Apr/2011
标准包装: 2,500
类型: 多压监控器
监视电压数目: 3
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 37 ms
电压 - 阀值: 1.11V,3.075V,可调
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: SOT-23-8 薄型,TSOT-23-8
供应商设备封装: TSOT-23-8
包装: 带卷 (TR)
其它名称: SP6336EK1-L-X-D-A/TR
SP6336EK1-L-X-D-A/TR-ND
X R P 6 3 3 6
T r i p l e μ P o w e r S u p e r v i s o r y C i r c u i t
w i t h W a t c h d o g a n d P o w e r F a i l
PIN DESCRIPTION
Name
V1
V2
PFI
V3
PFOB
GND
WDI
RST/RSTB
Pin Number
1
2
3
4
5
6
7
8
Description
First supply voltage input.
Also powers internal circuitry. Trip threshold voltage is internally set.
Second supply voltage input.
Trip threshold voltage internally set.
Power Fail Input pin.
Trip threshold is 0.5V. When the input voltage at the PFI pin is <0.5V, PFOB is low.
Connect to GND or V1 if not used.
Input for the third supply voltage. Trip threshold is 0.5V.
Power Fail Output pin.
Active low open drain output. When the input voltage at the PFI pin is <0.5V, PFOB is
low.
Common ground reference pin.
Watch-Dog Input pin.
When no transition is detected at the WDI pin for the duration of WDI timeout period,
reset is asserted. Leave open if not used. RST/RSTB outp4ut is used to signal watchdog
timeout overflow, and its output pulses high/low (depending on the active reset
polarity) for the reset timeout period after each watchdog timeout overflow. The
watchdog timer clears whenever the reset is asserted or manual reset is asserted or a
transition is observed at WDI pin. Watchdog timer functionality can be disabled by
leaving this input floating.
Reset output.
Open-Drain or CMOS, active high or low. Reset is asserted when any of the three supply
inputs is below its trip threshold. It stays asserted for 200 ms (typical / default) after
the last supply input traverses its trip threshold. Reset is guaranteed to be in the
correct state for V1>0.9V. RST/RSTB asserts when V1 or V2 or V3 drop below their
corresponding reset thresholds, or the watchdog timer triggers a reset. RST/RSTB
remains asserted for the reset timeout period after V1 and V2 and V3 exceed their
corresponding reset thresholds. Open drain outputs require an external pull-up resistor.
CMOS outputs are referenced to V1.
? 2011 Exar Corporation
5/10
Rev. 1.0.0
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