参数资料
型号: XRP7714ILB-F
厂商: Exar Corporation
文件页数: 19/29页
文件大小: 1009K
描述: IC REG 5OUT BCK/LINEAR 40TQFN
产品培训模块: Powering VLSI Based Systems
特色产品: XRP7714 PWM Step-Down DC/DC Controller
标准包装: 490
系列: PowerXR
拓扑: 降压(降压)同步(4),线性(LDO)(1)
功能: 任何功能
输出数: 5
频率 - 开关: 1.5MHz
电压/电流 - 输出 1: 控制器
电压/电流 - 输出 2: 控制器
电压/电流 - 输出 3: 控制器
带 LED 驱动器:
带监控器:
带序列发生器:
电源电压: 4.75 V ~ 25 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN(6x6)
包装: 托盘
配用: 1016-1350-ND - EVAL BAORD FOR XRP7714
1016-1344-ND - IN-SOCKET PROG BRD VIA USB/GUI
其它名称: 1016-1351
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?2011 Exar Corporation
19/29
Rev. 1.1.6
SOFT-STOP
The SET_PD_FALL_CHx register is a 16 bit register. This register specifies the soft-stop delay and
ramp (fall-time) characteristics for when the chip receives a channel disable indication from the
Host to shutdown the channel.
Bits [15:10] specify the delay after disabling a channel but before starting the shutdown of the
channel; where each bit represents 250祍 steps. Bits [9:0] specify the fall time of the channel;
these 10 bits define the number of microseconds for each 50mV increment to reach the discharge
threshold.
DELAY
Fall Time
Bit [10:15]
Bit [0:9]
Vout
Enable
Signal
PD_DELAY_CHx
REGISTER
 
Fig. 25: Channel Soft-Stop Sequence
POWER GOOD FLAG
The XRP7714 allows the user to set the upper and lower bound for a power good signal per
channel.     The     SET_PWRG_TARG_MAX_CHx     register     sets     the     upper     bound,     the
SET_PWRG_TARG_MIN_CHx register sets the lower bound. Each register has a 20mV LSB
resolution. When the output voltage is within bounds the power good signal is asserted high.
Typically the upper bound should be lower than the over-voltage threshold. In addition, the power
good signal can be delayed by a programmable amount set in the SET_PWRGD_DLY_CHx register.
The power good delay is only set after the soft-start period is finished. If the channel has a pre-
charged condition that falls into the power good region, a power good flag is not set until the soft-
start is finished.
PWM SWITCHING FREQUENCY
The PWM switching frequency is set by choosing the corresponding oscillator frequency and clock
divider ratio in the SET_SW_FREQUENCY register. Bits [6:4] set the oscillator frequency and bits
[2:0] set the clock divider. The tables below summarize the available Main Oscillator and PWM
switching frequency settings in the XRP7714.
Main Oscillator Frequency
SET_SW_FREQUENCY[6:4]
000
001
010
011
100
101
110
111
M  in
ill    r Fr
n
48MHz    44.8MHz   41.6MHz   38.4MHz   35.2MHz    32MHz    28.8Mhz   25.6MHz
T
20.8ns     22.3ns
24ns
26ns
28.4ns    31.25ns    34.7ns
39ns
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