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参数资料
| 型号： | XRT83D10IWTR-F |
| 厂商： | Exar Corporation |
| 文件页数： | 5/18页 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1 SGL 28SOJ |
| 标准包装： | 1,000 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 1/1 |
| 规程： | T1，E1 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-BSOJ |
| 供应商设备封装： | 28-SOJ |
| 包装： | 带卷 (TR) |
xr
XRT83D10
SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
REV. 1.0.3
13
occur.Jitter attenuator is no longer attenuating input jitter.(This signal is asserted until normal operation
resumes.)
1.4
ALARMS AND MAINTENANCE:
1.4.1
Loss of Signal:
A digital loss of signal (DLOS =1) is indicated if 175±75 or more consecutive 0s occur in the receive data
stream during DS1 operation.During CEPT operation, a DLOS is indicated when 32 or more consecutive 0s
occur in the receive data stream.DLOS is the deactivated when the ones density exceeds 12.5% and there are
no more than 100 consecutive 0s for DS1 and 16 consecutive 0s for CEPT, signifying the return of good
signal.DLOS deactivation monitors the data in a fixed 32-bit window.Each window must have at least four 1s
with no more than 15 consecutive 0s. Upon DLOS detection, RCLK is phase-locked to the external clock
(ExCLK) so that other system devices slaved to the line clock continue to operate without instantaneous phase
hits or discontinuities. Either an analog loss of signal (ALOS) or a digital loss of signal (DLOS) activates the
RLOS output pin.
1.4.2
Loss of Clock Signal (CLKLOS):
A loss of clock signal (CLKLOS =1) is indicated if either the transmit clock (TCLK) or the smoothing clock
(SCLK) output of the jitter attenuator is absent.If the jitter attenuator is placed in the transmit path, the SCLK is
monitored.If the jitter attenuator is not placed in the transmit path, TCLK or Remote Loopback Clock is
monitored.For every ten clock periods of the ExCLK oscillator clock, a strobe is generated.If a single transmit
clock period occurs between strobes, then CLKLOS = 0. If no transmit clock period occurs between strobes,
then CLKLOS = 1 and the output drivers ((TTIP and TRING) are placed into a high-impedance state and no
data is transmitted.
1.4.3
AIS (TAOS) Generator:
When the transmit all ones (TAOS = 1) signal is set, a continuous stream of bipolar 1s is transmitted onto the
line synchronous with ExCLK. The TPDATA and TNDATA inputs are ignored during this mode. If the RLOS
output is externally connected to the TAOS input, an RLOS error initiates a transmit all 1s signal as long as
RLOS = 1.Also, TAOS input is ignored when a remote loopback is selected. There is no microprocessor input
for the TAOS input, i.e., any change on the TAOS pin is fed directly into the device and is not impeded by the
CS function.
1.5
LOOPBACKS:
The XRT83D10 has three independent loopback paths, which are activated as shown in Figure 9.
NOTE: During Remote Loopback, TAOS is ignored.
A local loopback (LP1) connects the jitter attenuator’s output clock and data to the receive clock and data
output pins. MODE1:2 = 01 must be selected for this loopback to operate (jitter attenuator in the transmit path).
Valid transmit output data continues to be sent to the network. However, if the transmit all 1s (TAOS =1) is
TABLE 9: LOOPBACK CONTROL
OPERATION
SYMBOL
LOOPA
LOOPB
Normal
-
0
Digital Local loopback
LP3
0
1
Remote Loopback
LP2*
1
0
Local Loopback
LP1
1
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