参数资料
| 型号： | XRT83L34IV |
| 厂商： | Exar Corporation |
| 文件页数： | 24/99页 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1/J1 QUAD 128TQFP |
| 标准包装： | 72 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 4/4 |
| 规程： | T1，E1，J1 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 托盘 |
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XRT83L34
xr
REV. 1.0.1
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
27
In Host mode the programming is achieved through the corresponding interface control bits, the state of the
CLKSEL[2:0] control bits and the state of the MCLKRATE interface control bit.
RECEIVER
RECEIVER INPUT
At the receiver input, a cable attenuated AMI signal can be coupled to the receiver through a capacitor or a 1:1
transformer. The input signal is first applied to a selective equalizer for signal conditioning. The maximum
equalizer gain is up to 36dB for T1 and 43dB for E1 modes. The equalized signal is subsequently applied to a
peak detector which in turn controls the equalizer settings and the data slicer. The slicer threshold for both E1
and T1 is typically set at 50% of the peak amplitude at the equalizer output. After the slicers, the digital
representation of the AMI signals are applied to the clock and data recovery circuit. The recovered data
subsequently goes through the jitter attenuator and decoder (if selected) for HDB3 or B8ZS decoding before
being applied to the RPOS_n/RDATA_n and RNEG_n/LCV_n pins. Clock recovery is accomplished by a digital
phase-locked loop (DPLL) which does not require any external components and can tolerate high levels of
input jitter that meets or exceeds the ITU-G.823 and TR-TSY000499 standards.
In Hardware mode only, all receive channels are turned on upon power-up and are always on. In Host mode,
each receiver channel can be individually turned on or off with the respective channel RXON_n bit. See
TABLE 1: MASTER CLOCK GENERATOR
MCLKE1
K
HZ
MCLKT1
K
HZ
CLKSEL2
CLKSEL1
CLKSEL0
MCLKRATE
MASTER CLOCK
K
HZ
2048
0
2048
0
1
1544
2048
1544
0
2048
1544
0
1
1544
0
1
0
2048
1544
0
1
1544
8
x
0
1
0
2048
8
x
0
1
0
1
1544
16
x
0
1
0
2048
16
x
0
1
1544
56
x
1
0
2048
56
x
1
0
1
1544
64
x
1
0
1
0
2048
64
x
1
0
1
1544
128
x
1
0
2048
128
x
1
0
1
1544
256
x
1
0
2048
256
x
1
1544
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT83L34IV-F | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| XRT83L34IVTR | 功能描述:外围驱动器与原件 - PCI RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT83L34IVTR-F | 功能描述:外围驱动器与原件 - PCI RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT83L38 | 制造商:EXAR 制造商全称:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83L38_07 | 制造商:EXAR 制造商全称:EXAR 功能描述:OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
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