参数资料
型号: XRT83SL38IB-F
厂商: Exar Corporation
文件页数: 1/88页
文件大小: 0K
描述: IC LIU SH T1/E1/J1 OCTAL 225BGA
标准包装: 84
类型: 线路接口装置(LIU)
驱动器/接收器数: 8/8
规程: T1,E1,J1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 225-BGA
供应商设备封装: 225-BGA(19x19)
包装: 托盘
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XRT83SL38
OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER
JUNE 2007
REV. 1.0.2
GENERAL DESCRIPTION
The XRT83SL38 is a fully integrated Octal (eight
channel)
short-haul
line
interface
unit
for
T1
(1.544Mbps) 100
Ω, E1 (2.048Mbps) 75Ω or 120Ω, or
J1 110
Ω applications.
In T1 applications, the XRT83SL38 can generate five
transmit pulse shapes to meet the short-haul Digital
Cross-Connect (DSX-1) template requirements. It
also
provides
programmable
transmit
pulse
generators for each channel that can be used for
output
pulse
shaping
allowing
performance
improvement over a wide variety of conditions (The
arbitrary pulse generators are available in both T1
and E1 modes).
The XRT83SL38 provides both a parallel Host
microprocessor interface as well as a Hardware
mode for programming and control.
Both the B8ZS and HDB3 encoding and decoding
functions are selectable as well as AMI. An on-chip
crystal-less jitter attenuator with a 32 or 64 bit FIFO
can be placed either in the receive or the transmit
path with loop bandwidths of less than 3Hz. The
XRT83SL38 provides a variety of loop-back and
diagnostic features as well as transmit driver short
circuit detection and receive loss of signal monitoring.
It supports internal impedance matching for 75
Ω,
100
Ω, 110Ω and 120Ω for both transmitter and
receiver. In the absence of the power supply, the
transmit outputs and receive inputs are tri-stated
allowing
for
redundancy
applications
The
chip
includes an integrated programmable clock multiplier
that can synthesize T1 or E1 master clocks from a
variety of external clock sources.
APPLICATIONS
T1 Digital Cross-Connects (DSX-1)
ISDN Primary Rate Interface
CSU/DSU E1/T1/J1 Interface
T1/E1/J1 LAN/WAN Routers
Public switching Systems and PBX Interfaces
T1/E1/J1 Multiplexer and Channel Banks
Features (See Page 2)
FIGURE 1. BLOCK DIAGRAM OF THE XRT83SL38 T1/E1/J1 LIU (HOST MODE)
One of Eight channels, CHANNEL_n - (n= 0:7)
HW/HOST
WR_R/W
RD_DS
ALE-AS
CS
RDY_DTACK
INT
ICT
TPOS_n/TDATA_n
TNEG_n/CODES_n
TCLK_n
RCLK_n
RNEG_n/LCV_n
RPOS_n/RDATA_n
RLOS_n
RTIP_n
RRING_n
MASTER CLOCK SYNTHESIZER
QRSS
PATTERN
GENERATOR
DMO_n
TTIP_n
TRING_n
TXON_n
HDB3/
B8ZS
ENCODER
TX/RX JITTER
ATTENUATOR
TIMING
CONTROL
TX FILTER
& PULSE
SHAPER
LINE
DRIVER
DRIVE
MONITOR
LOCAL
ANALOG
LOOPBACK
REMOTE
LOOPBACK
DIGITAL
LOOPBACK
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
TIMING &
DATA
RECOVERY
PEAK
DETECTOR
& SLICER
QRSS
DETECTOR
NETWORK
LOOP
DETECTOR
RX
EQUALIZER
CONTROL
AIS
DETECTOR
LOS
DETECTOR
LBO[3:0]
LOOPBACK
ENABLE
JA
SELECT
NLCD ENABLE
QRSS ENABLE
μPTS1
μPTS2
D[7:0]
μPCLK
A[7:0]
RESET
MICROPROCESSOR CONTROLLER
TEST
DFM
TAOS
ENABLE
MCLKE1
MCLKT1
MCLKOUT
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