参数资料
| 型号： | XRT91L30IQTR |
| 厂商： | Exar Corporation |
| 文件页数： | 3/40页 |
| 文件大小： | 0K |
| 描述： | IC TXRX SONET/SDH 8BIT 64QFP |
| 标准包装： | 1,000 |
| 类型： | 收发器 |
| 规程： | SONET/SDH |
| 电源电压： | 3.3V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-FQFP |
| 供应商设备封装： | 64-PQFP（10x10） |
| 包装： | 带卷 (TR) |
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XRT91L30
7
REV. 1.0.2
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
TRANSMITTER SECTION
NAME
LEVEL
TYPE
PIN
DESCRIPTION
TXDI0
TXDI1
TXDI2
TXDI3
TXDI4
TXDI5
TXDI6
TXDI7
LVTTL,
LVCMOS
I
58
57
56
55
54
53
51
50
Transmit Parallel Data Input
Transmit Parallel Clock Output Operation
The 77.76 Mbps (STS-12/STM-4) / 19.44 Mbps (STS-3/STM-1)
8-bit parallel transmit data should be applied to the transmit
parallel bus and simultaneously referenced to the rising edge of
the TXPCLK_IO clock output. The 8-bit parallel interface is mul-
tiplexed into the transmit serial output interface with the MSB
first (TXDI[7:0]).
Alternate Transmit Parallel Clock Input Operation
When operating is this mode, TXPCLK_IO is no longer a paral-
lel clock output reference but reverses direction and serves as
the parallel transmit clock input reference for the PISO (Parallel
Input to Serial Output) block. The 77.76 Mbps (STS-12/STM-4)
/ 19.44 Mbps (STS-3/STM-1) 8-bit parallel transmit data should
be applied to the transmit parallel bus and simultaneously refer-
enced to the rising edge of the TXPCLK_IO clock input.
TXOP
TXON
LVPECL Diff
O
5
6
Transmit Serial Data Output
The transmit serial data stream is generated by multiplexing the
8-bit parallel transmit data input into a 622.08 Mbps STS-12/
STM-4 or 155.52 Mbps STS-3/STM-1 serial data stream.
TXPCLK_IO
LVTTL,
LVCMOS
I/O
49
Transmit Parallel Clock Input/Output (77.76/19.44 MHz)
Transmit Parallel Clock Output Operation
When the PIO_CTRL pin 48 is asserted "High," this pin will out-
put a 77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-
1) clock output reference for the 8-bit parallel transmit data
input TXDI[7:0]. This clock is used by the framer/mapper device
to present the TXDI[7:0] data which the XRT91L30 will latch on
the rising edge of this clock. This enables the framer/mapper
device and the XRT91L30 transceiver to be in synchronization.
Alternate Transmit Parallel Clock Input Operation
When the PIO_CTRL pin 48 is asserted "Low," this pin will
accept a 77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/
STM-1) clock input reference for the 8-bit parallel transmit data
input TXDI[7:0]. The XRT91L30 will latch data at TXDI[7:0] on
the rising edge of this clock. This has the enormous advantage
of enabling the framer/mapper device transmit timing to be syn-
chronized with the transceiver transmit timing.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT91L30IQTR-F | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| XRT91L31 | 制造商:EXAR 制造商全称:EXAR 功能描述:STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L31_08 | 制造商:EXAR 制造商全称:EXAR 功能描述:STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER |
| XRT91L31ES | 功能描述:总线收发器 RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| XRT91L31IQ | 功能描述:网络控制器与处理器 IC SONET/SDH, FULL DPLX 3.3V I/O, LOS, CMU RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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