参数资料
| 型号： | XRT91L80IB-F |
| 厂商： | Exar Corporation |
| 文件页数： | 8/46页 |
| 文件大小： | 0K |
| 描述： | IC TXRX SONET/SDH 4BIT 196STBGA |
| 产品变化通告： | XRT91L80IB Obsolescence 6/Sept/2010 |
| 标准包装： | 126 |
| 类型： | 收发器 |
| 规程： | SONET/SDH |
| 电源电压： | 3.3V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 196-LFBGA |
| 供应商设备封装： | 196-STBGA（12x12） |
| 包装： | 托盘 |
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XRT91L80
xr
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
REV. 1.0.0
14
2.0
RECEIVE SECTION
The receive section of XRT91L80 includes the differential inputs RXIP/N, followed by the clock and data
recovery unit (CDR) and receive serial-to-parallel converter (SIPO). The receiver accepts the high speed Non-
Return to Zero (NRZ) serial data at 2.488/2.666 Gbps through the differential input interfaces RXIP/N. The
clock and data recovery unit recovers the high-speed receive clock from the incoming scrambled NRZ data
stream. The recovered serial data is converted into 4-bit-wide 622.08/666.51 Mbps parallel data and presented
to the RXD[3:0]P/N LVDS parallel interface. A divide-by-4 version of the high-speed recovered clock,
RXPCLKOP/N, is used to synchronize the transfer of the 4-bit RXDO[3:0]P/N data with the receive portion of
the upstream device. Upon initialization or loss of signal or loss of lock the 77.76/155.52 MHz (83.31/166.63
MHz) external local reference clock is used to start-up the clock recovery phase-locked loop for proper
operation. A special loop-back feature can be configured when parallel remote loopback (RLOOPP) is used in
conjunction with de-jittered loop-time mode that allows the re-transmitted data to comply with ITU and Bellcore
jitter generation specifications.
2.1
Receive Serial Input
The receive serial CML inputs are applied to RXIP/N. The receive serial inputs can be AC or DC coupled to an
optical module or an electrical interface. A simplified AC coupled block diagram is shown in Figure 4.
NOTE: Some optical modules integrate AC coupled capacitors within the module. If so, the external AC coupled capacitors
are not necessary and can be excluded.
The 2.488/2.666 Gbps high-speed differential CML RXIP/N input swing characteristics is shown in Table 2.
FIGURE 4. RECEIVE SERIAL INPUT INTERFACE BLOCK
TABLE 2: DIFFERENTIAL CML INPUT SWING PARAMETERS
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNITS
V
INDIFF
Differential Input Voltage Swing
200
1000
mV
V
INSE
Single-Ended Input Voltage Swing
100
500
mV
V
INBIAS
Input Bias Range (AC Coupled)
1.0
1.4
V
RDIFF
Differential Input Resistance
75
125
XRT91L80
STS-48/
STM-16
Transceiver
Optical Module
0.1
F
0.1
F
RXIP
RXIN
Optical Fiber
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相关代理商/技术参数 |
参数描述 |
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| XRT91L81 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L81IB | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82ES | 功能描述:总线收发器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| XRT91L82IB | 功能描述:总线收发器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
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