- 您现在的位置：买卖IC网 > PDF目录48100 > YGV617B CRT OR FLAT PNL GRPH DSPL CTLR, PQFP144 PDF资料下载
参数资料
| 型号： | YGV617B |
| 元件分类： | 显示控制器 |
| 英文描述： | CRT OR FLAT PNL GRPH DSPL CTLR, PQFP144 |
| 封装： | PLASTIC, SQFP-144 |
| 文件页数： | 8/12页 |
| 文件大小： | 140K |
| 代理商： | YGV617B |
5
YGV617B
9 WAIT (O : Pull Up, 3 state output)
This is the data wait signal outputted to CPU. When CS pin is active, this pin outputs WAIT signal responding to the
RD or A0/WR1 and WR0 signals, and then clears the WAIT signal when the CPU has become accessible.
When CS pin is not active, this pin becomes high impedance state.
When CS pin is active and RD or A0/WR1 and WR0 pins are not active, the level of this pin becomes high.
Some CPU must use READY signal instead of this signal.
State of WAIT signal at write access
9 INT (O : Open drain output)
Outputs an interrupt request signal to CPU. This signal becomes active when the internal state of AVDP3 coincides
with the conditions set in the registers. It is reset when registers of AVDP3 have been accessed.
9 LWD (I)
This signal selects the width of data bus according to CPU. When high level signal is inputted, this device complies
with 16 bit system, or when low level signal is inputted, it complies with 8 bit system.
9 RESET (I : Pull Up)
This pin accepts an initial reset signal. Internal registers of AVDP3 is cleared to "0" when this signal has been
inputted. (Some registers are loaded with initial value.) Make sure to input the reset signal at power on.
9 DREQ (O)
Outputs command data request signal to an external DMA controller.
9 DACK (I : Pull Up)
When an external DMA controller has received DREQ signal, it returns command data transfer permit signal to this
device through this pin.
<Video Memory Interface>
9 VA9-VA0 (O)
These pins comprise an address bus for VRAM. This bus outputs low address and column address of DRAM used by
AVDP3 based on time sharing. This pin becomes high impedance when in VRAM halt state.
9 VD15-VD0 (I/O : Pull Up)
These pins comprise an data bus for VRAM. Data of DRAM used by AVDP3 are transferred through this bus. This
pin becomes high impedance when in VRAM halt state.
9 RAS (O)
This pin outputs DRAM row address strobe signals for VRAM. This pin becomes high impedance when in VRAM
halt state.
9 CAS1,0 (O)
These pins output DRAM column address strobe signals for VRAM. CAS1 and CAS0 are respectively related to data
buses VD15-8 and VD7-0. These pins become high impedance when in VRAM halt state.
Hi-Z
CS
A0/WR1,WR0
D15-0
A6-1
WAIT
VALID
相关PDF资料 |
PDF描述 |
|---|---|
| YGV618-F | CRT OR FLAT PNL GRPH DSPL CTLR, PQFP160 |
| YGV618 | ADVANVED VIDEO DISPLAY PROCESSOR 5 |
| YGV618 | Advanced Video Display Processor 5(高级视频显示处理器5) |
| YGV618 | CRT OR FLAT PNL GRPH DSPL CTLR, PQFP160 |
| YGV619-SZ | SPECIALTY CONSUMER CIRCUIT, PQFP240 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| YGV618 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ADVANVED VIDEO DISPLAY PROCESSOR 5 |
| YGV619 | 制造商:LSI 制造商全称:LSI 功能描述:Advanced Video Display Processor 6 |
| YGV627 | 制造商:YAMAHA 制造商全称:YAMAHA CORPORATION 功能描述:AVDP3E - Advanced Video Display processor 3 Enhanced |
| YGV628B | 制造商:YAMAHA 制造商全称:YAMAHA CORPORATION 功能描述:AVDP7 Advanced Video Display Processor 7 |
| YGV629 | 制造商:YAMAHA 制造商全称:YAMAHA CORPORATION 功能描述:VC1 Video Controller 1 |
发布紧急采购，3分钟左右您将得到回复。