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参数资料
| 型号： | YGV619-S |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP240 |
| 封装： | SQFP-240 |
| 文件页数： | 8/23页 |
| 文件大小： | 521K |
| 代理商： | YGV619-S |
YGV619
16
SDRAM interface ((((Measurement condition: CL====20000 PF))))
No.
Parameter
Symbol
Min.
Typ.
Max.
Unit
Note
1
SDCLK: cycle time
tcSDCLK
12.5
1
2
SDCLK: clock width
twSDCLK
5
1
3
SDQ[31:0]: input data setup time
tsSDQ
4
1
4
SDQ[31:0]: input data hold time
thSDQ
1
5
Output Signals: hold time
thSDO
2
1,2
6
Output Signals: delay time
tdSDO
10
ns
1,2
5 SDRAM Mode Register Setting Data
Read/Write Mode
: Burst Read and Burst Write
CAS Latency
: 2
Wrap Type
: Sequential
Burst Length
: 2
5 Command interval Note 3)
RAS cycle time (tRC)
Six or less cycles
(75 ns or less when SDCLK frequency is 80 MHz)
RAS precharge time (tRP)
Two or less cycles (25 ns or less when SDCLK frequency is 80 MHz)
RAS active time (tRAS)
Four or less cycles (50 ns or less when SDCLK frequency is 80 MHz)
RAS
- CAS
delay
time
(
tRCD)
Two or less cycles (25 ns or less when SDCLK frequency is 80 MHz)
Note 1)
PLL must be in stabilized state.
Note 2)
Output Signals are those outputted from the following pins: SA[12:0], SBA[1:0], SDQ[31:0], SCS
, RAS, CAS,
WE , DQM[3:0]
Note 3)
Conditions of SDRAM to be chosen.
SDCLK
SDQ[31:0] (input )
Output Signals
1
3
4
5
6
22
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