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参数资料
| 型号： | YMF715E-S |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封装： | SQFP-100 |
| 文件页数： | 16/53页 |
| 文件大小： | 455K |
| 代理商： | YMF715E-S |
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YMF715E
May 21, 1998
-23-
8-1. Partial Power Down Mode
Functional blocks comprising OPL3-SA3 which are shown in Fig.8-1, are designed so they can be
disabled independent of each other. SA3 control register, index 12h and 13h, implements these
controls (see section 9-1-5).
,
blocks in the above diagram show those that can be disabled/enabled. Note, however,
the OPL3-SA3 dissipates more power with all these blocks “partial power down”ed than that can be
achieved in “power save mode 2”.
In this mode, master volume is not muted, so all analog input sources and enabled digital sources (i.e.
FM, SB, WSS etc.) can be heard.
Note :
AUX2 inputs are exceptions in this regard since setting FM-DAC at index 13h of SA3 Control
Register inhibits the inputs altogether.
8-2. Power Save Mode
SA3 control register, index 01h, PSV and PDX bits, implement these controls.
Clock generator can be controlled under either two options.
(i) Power Save Mode 1 (Clock Generator Control : Disabled (stop))
(PSV=PDX=1)
It is necessary to take some time before clock oscillation to stabilize. Power dissipation of digital
portion becomes about 100uA(typ.), and that of analog portion becomes about 5mA(typ.).
(ii) Power Save Mode 2 (Clock Generator Control : Enabled (crystals keep on oscillating))
(PSV=1, PDX=0)
Leaving power save mode gets the OPL3-SA3 back into function instantly. Power dissipation of
digital portion becomes about 10mA(typ.), and that of analog portion becomes about 5mA(typ.).
In these power save modes, the OUTL/R pins will keep the VREF voltage. During these modes,
master volume is automatically muted, so all audio sources can not heard. After resuming from these
modes, master volume is still muted.
8-3. Global Power Down Mode
(PDN=PDX=1)
This mode is to minimize power dissipation by stopping all the function of OPL3-SA3. It is
necessary to take some time before clock oscillation to stabilize. Total dissipation becomes about
10uA(typ.).
VREF voltage slowly decays to ground on transition into this mode, and quickly returns to VREF on
transition from this mode. During this mode, master volume is automatically muted, so all audio
sources can not heard. After resuming from this mode, master volume is still muted.
相关PDF资料 |
PDF描述 |
|---|---|
| YMF715E | OPL3 Single-Chip Audio System 3(OPL3 单片音频系统3) |
| YMF721-S | SPEECH SYNTHESIZER, PQFP100 |
| YMF721 | FM + Wavetable Synthesizer LSI |
| YMF724F-V | SPECIALTY CONSUMER CIRCUIT, PQFP144 |
| YMF724 | high performance audio controller for the PCI Bus |
相关代理商/技术参数 |
参数描述 |
|---|---|
| YMF721 | 制造商:LSI 制造商全称:LSI 功能描述:FM + Wavetable Synthesizer LSI |
| YMF724 | 制造商:YAMAHA 制造商全称:YAMAHA CORPORATION 功能描述:high performance audio controller for the PCI Bus |
| YMF724F | 制造商:YAMAHA 制造商全称:YAMAHA CORPORATION 功能描述:high performance audio controller for the PCI Bus |
| YMF724F-V | 制造商:YAMAHA 制造商全称:YAMAHA CORPORATION 功能描述:high performance audio controller for the PCI Bus |
| YMF740C | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DS-1L |
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