
YMF740C
January 14, 1999
-19-
48-49h: DS-1L Control Register
Read / Write
Default: 0001h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
-
CRST
b0................CRST: AC’97 Software Reset Signal Control
This bit controls the CRST# signal.
“0”: Inactive (CRST#=High)
“1”: Active (CRST#=Low)
(default)
4A-4Bh: DS-1L Power Control Register
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
PR7
PR6
PR5
PR4
PR3
PR2
PR1
PR0
-
PSN
PSL1
PSL0 DPLL1 DPLL0 DMC
b0................DMC: Disable Master Clock Oscillation
Setting this bit to “1” disables the oscillation of the Master Clock (24.576 MHz).
“0”: Normal
(default)
“1”: Disable
b1................DPLL0: Disable PLL0 Clock Oscillation
Setting this bit to “1” disables the oscillation of PLL for the Legacy Audio function.
“0”: Normal
(default)
“1”: Disable
b2................DPLL1: Disable PLL1 Clock Oscillation
Setting this bit to “1” disables the oscillation of PLL for the PCI Audio function.
“0”: Normal
(default)
“1”: Disable
b3................PSL0: Power Save Legacy Audio Block 0
Setting this bit to “1” stops providing the clock with the Legacy Audio function block 0.
This block
includes FM Synthesizer and SB Pro engines.
“0”: Normal
(default)
“1”: Power Save
b4................PSL1: Power Save Legacy Audio Block 1
Setting this bit to “1” stops providing the clock with the Legacy Audio function block 1.
This block
includes MPU401 and Joystick.
“0”: Normal
(default)
“1”: Power Save