
YMF752
July 2, 1999
7
SYSTEM CONNECTION DIAGRAM
1) Power and Ground
To get the most out of analog performance, it is necessary to split the ground into analog and digital blocks.
Analog ground and digital ground earth at one point closed to the initial ground supply of the board. The
layout of the ground pattern should be designed as large as possible and the impudence should be reduced to
prevent from receiving ambient noise. In addition, use 0.1
mF and 47mF capacitors to connect between the
analog voltage pin and the analog ground as well as between the digital supply pin and the digital ground.
2) Reference Voltage
As the reference voltage determines all analog signals’ reference levels of YMF752, noise generated from
the reference voltage could affect the YMF752’s analog performance. To stabilize the YMF752’s reference
voltage, insert a 0.1
mF ceramic capacitor in parallel with a 10mF capacitor between Vref pin and the ground.
The 0.1
mF ceramic capacitor should be designed as close to the Vref pin as possible
3) Master Clock
To suppress the master clock from affecting its surroundings, it is recommended to keep the master clock
guarded on the ground so the noise can be reduced.
4) Unused Analog Input / Output pins
For the unused analog input pins, short them through a 0.1
mF ceramic capacitor to the analog ground. For
the unused analog output pins, they should be left opened.
PC_BEEP
AUX_L
PHONE
SDAT
A_
IN
M
O
NO_
O
UT
LIN
E
_OU
T
_R
LIN
E
_OU
T
_L
SDAT
A_
O
U
T
BI
T
_
CL
K
SYNC
RESET
#
X
T
L_OU
T
X
T
L_IN
VIDEO_L
AUX_R
CD_L
YMF752-S
VIDEO_R
MIC1
CD_R
LINE_IN_L
LINE_IN_R
CAP1
CAP3
CAP2
L-ch LINE Out
R-ch LNLVL Out
R-ch LINE Out
CAP4
AVdd1,2
+5.0V
DGND AGND
AVss1,2
PC Beep
L-ch AUX
Phone
L-ch Video
R-ch AUX
L-ch CD
R-ch Video
MIC
R-ch CD
L-ch Line IN
R-ch Line IN
CD_GND
CD Ground
+3.3V
Mono Out
L-ch LNLVL Out
LN
LV
L_OU
T
_L
LN
LV
L_OU
T
_R
EAPD
ID0#
ID1#
EAPD
SDATA IN
BIT CLK
RESET#
SYNC
SDATA OUT
Vref
DVdd1,2
ENABL
E
DVss1,2
V
refout
MIC2