参数资料
型号: YMF807
元件分类: 消费家电
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封装: LEAD FREE, SQFP-48
文件页数: 3/18页
文件大小: 1793K
代理商: YMF807
YMF807
11
CPU Interface
Parameter
Symbol
Min.
Typ.
Max.
Unit
SCK Period
Tsck_period
50
ns
SCK “L” Pulse Width (*1)
Tsck_low
24
ns
SCK “H” Pulse Width (*1)
Tsck_high
24
ns
SCK Rise Time
Tsck_rise
5
ns
SCK Fall Time
Tsck_fall
5
ns
/SS “H” Pulse Width (*2)
Tssn_high
650 / 50
ns
/SS Rise Time
Tssn_rize
5
ns
/SS Fall Time
Tssn_fall
5
ns
SI Rise Time
Tsi_rize
5
ns
SI Fall Time
Tsi_fall
5
ns
/SS Setup Time
Tssn_setup
15
ns
/SS Hold Time
Tssn_hold
5
ns
SI Setup Time
Tsi_setup
15
ns
SI Hold Time
Tsi_hold
5
ns
SO Output Delay 1 (SMODE= “0”)
Tso_delay1
12
ns
SO Output Delay 2 (SMODE= “0”)
Tso_delay2
21
ns
SO Output Delay 3 (SMODE= “0”)
Tso_delay3
12
ns
SO Output Delay 4 (SMODE= “1”)
Tso_delay4
12
ns
SO Output Delay 5 (SMODE= “1”)
Tso_delay5
21
ns
SO Output Delay 6 (SMODE= “1”)
Tso_delay6
12
ns
Conditions: TOP=-40 to 105℃, VDDIO=4.75 to 5.25[V], or VDDCORE=3.0 to 3.6[V], Capacitor load=50pF
IOH=-2.0mA, IOL=+2.0mA (S0 pin)
The measurement points are at VIH= 0.7×VDDIO, VIL=0.2×VDDIO, VOH=0.8×VDDIO, and
VOL=0.2×VDDIO
(*1) Tsck_low + Tsck_high should be more than Tsck_period(min.).
(*2) To read data from the control register by using IF Register (BANK1/#11 and #12), a pulse width of /SS (“H”)
between #11 access and #12 access is 650ns (min.). In other cases, it becomes 50ns (min.).
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