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参数资料
| 型号： | YMU759B-Q |
| 英文描述： | Stratix II FPGA 60K FBGA-1020 |
| 中文描述： | 通信集成电路 |
| 文件页数： | 4/18页 |
| 文件大小： | 363K |
| 代理商： | YMU759B-Q |
YMU759B
-12-
Parallel I/F
(write cycle)
Item
Symbol
Min.
Max.
Unit
Chip select width
TCSW
100
ns
Address setup time
TAS
10
ns
Address hold time
TAH
10
ns
Write pulse width
TWW
50
ns
Data setup time
TWDS
30
ns
Data hold time
TWDH
5
ns
Note: TOP=-20 ~ 85°C, VDD=3.0±0.3 V, Capacitor load=50 pF.
(Read cycle)
Item
Symbol
Min.
Max.
Unit
Chip select width
TCSR
100
ns
Address setup time
TAS
0
ns
Address hold time
TAH
0
ns
Read pulse width
TRW
80
ns
Read data access time
TACC
70
ns
Data hold time
TRDH
10
50
ns
Note: TOP=-20 ~ 85°C, VDD=3.0±0.3 V, Capacitor load=50 pF.
Write cycle
Note: TCSW, TWW, TWDH and TAH are defined with respect to the moment /CS or /WR becomes High level.
Measurement point
VIH = 0.7
× VDD
VIL = 0.2
× VDD
VOH= 0.8
× VDD
VOL = 0.4V
Valid
A0
TWDS
Invalid
/CS
/WR
Invalid
TWDH
TWW
TCSW
TAS
D0~D7
TAH
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