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参数资料
| 型号： | YTD421B |
| 厂商： | Yamaha Corporation |
| 元件分类： | 外设及接口 |
| 英文描述： | Single Supply RS232C Line Driver/Receiver(?????μ?o?RS232C ?o?????????¨???2???2??????) |
| 中文描述： | 单电源RS232C接口线路驱动器/接收器（单电源RS232C接口线收发器（2发2收）） |
| 文件页数： | 2/25页 |
| 文件大小： | 284K |
| 代理商： | YTD421B |
8
CHAPTER
3.
PIN
DESCRIPTIONS
3.2
Pin
F
unctions
3.2.1
Common
Section
Pin
No.
Pin
Name
I/O
F
unction
Remarks
9,13
V
DD
PWR
+5V65%
P
o
w
er
supply
1,16
V
SS
GND
Ground
11
RX
{
Connecting
external
resistor
15
CX1
{
Connecting
external
capacitor
1
18
CX2
{
Connecting
external
capacitor
2
10
SLEEP
IN
Sleep
Mo
de
\H":
Standb
y
(Lo
wp
o
w
er
consumption)
mo
de
\L":
Activ
emo
de
Note
1
Note
1:
When
making
SLEEP
pin
\H",
connects
it
to
VDDO
p
o
w
er
source
pin.
3.2.2
Receiv
er
Section
Pin
No.
Pin
Name
I/O
F
unction
Remarks
4
HRD
OUT
High
Pulse
of
Receiv
e
Data
Outputs
the
high
pulse
of
receiv
ed
AMI
signal.
Changes
the
output
t
yp e
b
y
setting
ODSEL
pin.
TTL
in
terface.
Note
2
3
LRD
OUT
Lo
w
Pulse
of
Receiv
e
Data
Outputs
the
lo
w
pulse
of
receiv
ed
AMI
signal.
Changes
the
output
t
yp e
b
y
setting
ODSEL
pin.
TTL
in
terface.
Note
2
20
LI1
IN
S/T
Line
Input
(p
ositiv
e)
Inputs
S/T
in
terface
data
through
a
pulse
transformer.
17
LI2
IN
S/T
Line
Input
(negativ
e)
Inputs
S/T
in
terface
data
through
a
pulse
transformer.
19
LICT
OUT
S/T
Line
Reference
Source
Output
Connects
to
the
pulse
transformer's
cen
ter
tap
5
ODSEL
IN
HRD,
LRD
Output
Select
\H":
HRD,
LRD
pin
normal
output
(p
ositiv
e
p
olarit
y)
\L":
HRD,
LRD
pin
op
en
drain
(negativ
e
p
olarit
y)
Note
3
Note
4
2
VDDO
PWR
P
o
w
er
Source
for
HRD,
LRD
pin
Connects
to
the
p
o
w
er
source
of
the
circuit
whic
h
HRD
pin
and
LRD
pin
are
connected
to.
It
enables
the
in
terface
with
+3.3V
circuit.
Note
2:
When
pulling
HRD
pin
and
LRD
pin
up
via
pull-up
resistors,
pulls
them
up
to
VDDO
p
o
w
er
source
pin.
Note
3:
When
making
ODSEL
pin
\H",
connects
it
to
VDDO
p
o
w
er
source
pin.
Note
4:
\p
ositiv
e
p
olarit
y"
means
the
condition
that
v
oltage
lev
el
=
\H"
when
logic
=
binary
\0".
\negativ
e
p
olarit
y"
means
the
condition
that
v
oltage
lev
el
=
\L"
when
logic
=
binary
\0".
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