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参数资料
| 型号： | ZL9101MIRZ-T |
| 厂商： | Intersil |
| 文件页数： | 6/19页 |
| 文件大小： | 0K |
| 描述： | DCDC DGTL PMBUS MODULE 12A 21QFN |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 500 |
| 系列： | ZL9101M |
| 类型： | 非隔离（POL） |
| 输出数： | 1 |
| 电压 - 输入（最小）： | 4.5V |
| 电压 - 输入（最大）： | 13.2V |
| Voltage - Output 1： | 0.6 ~ 4 V |
| 电流 - 输出（最大）： | 12A |
| 电源（瓦） - 制造商系列： | 48W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 21-QFN，变式 |
| 尺寸/尺寸： | 0.59" L x 0.59" W x 0.14" H（15.0mm x 15.0mm x 3.5mm） |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 85°C |
| 效率： | 95% |
| 电源（瓦特）- 最大： | 48W |
ZL9101M
Electrical Specifications V DD = 12 V, T A = -40°C to +85°C unless otherwise noted. Typical values are at T A = 25°C. Boldface limits apply
over the operating temperature range, -40°C to +85°C. (Continued)
MIN
TYP
MAX
PARAMETER
Voltage Change for Negative Load Step
CONDITIONS
Δ I OUT = 6A, slew rate = 2.5A/ μ s,
V OUT = 1.2V, C OUT = 3000μF
(Note 9)
–
(Note 10)
3
(Note 9)
–
UNIT
%
OSCILLATOR AND SWITCHING CHARACTERISTICS (Note 11)
Switching Frequency Range
500
571
1000
kHz
Maximum PWM Duty Cycle
Minimum SYNC Pulse Width
Input Clock Frequency Drift Tolerance
Factory setting
External clock source
95
150
-13
–
–
–
–
–
13
%
ns
%
LOGIC INPUT/OUTPUT CHARACTERISTICS (Note 11)
Logic Input Bias Current
Logic Input Low, V IL
Logic Input High, V IH
Logic Output Low, V OL
Logic Output High, V OH
EN, PG, SCL, SDA pins
I OL ≤ 4mA (Note 17)
I OH ≥ -2mA (Note 17)
-10
–
2.0
–
2.25
–
–
–
–
–
10
0.8
–
0.4
–
μA
V
V
V
V
FAULT PROTECTION CHARACTERISTICS (Note 11)
UVLO Threshold Range
UVLO Set-point Accuracy
UVLO Hysteresis
Configurable via I 2 C/SMBus
Factory setting
2.85
-150
–
–
–
3
16
150
–
V
mV
%
UVLO Delay
Configurable via I 2 C/SMBus
0
–
–
–
100
2.5
%
μs
Power Good V OUT Threshold
Power Good V OUT Hysteresis
Power Good Delay (Note 16)
VSEN Undervoltage Threshold
VSEN Overvoltage Threshold
Factory setting
Factory setting
Configurable via I 2 C/SMBus
Factory setting
Configurable via I 2 C/SMBus
Factory setting
–
–
0
–
0
–
90
5
–
85
–
115
–
–
200
–
110
–
% V OUT
%
ms
% V OUT
% V OUT
% V OUT
VSEN Undervoltage Hysteresis
Configurable via I 2 C/SMBus
0
–
–
5
115
–
% V OUT
% V OUT
VSEN Undervoltage/Overvoltage Fault Response
Time
Thermal Protection Threshold
(Controller Junction Temperature)
Thermal Protection Hysteresis
Factory setting
Configurable via I 2 C/SMBus
Factory setting
Configurable via I 2 C/SMBus
–
5
–
-40
–
16
–
125
–
15
–
60
–
125
–
μs
μs
°C
°C
°C
NOTES:
9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
10. Parameters with TYP limits are not production tested unless otherwise specified.
11. Parameters are 100% tested for internal controller prior to module assembly.
12. V OUT measured at the termination of the FB+ and FB- sense points.
13. The device requires a delay period following an enable signal and prior to ramping its output. Precise timing mode limits this delay period to
approximately 2ms, where in normal mode it may vary up to 4ms.
14. Precise ramp timing mode is only valid when using the EN pin to enable the device rather than PMBus enable.
15. The devices may require up to a 4ms delay following the assertion of the enable signal (normal mode) or following the de-assertion of the enable
signal.
16. Factory setting for Power Good delay is set to the same value as the soft-start ramp time.
17. Nominal capacitance of logic pins is 5pF.
6
FN7669.4
January 20, 2012
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