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| 型号： | ZM7316G-65503-B1 |
| 厂商： | Power-One |
| 文件页数： | 26/33页 |
| 文件大小： | 0K |
| 描述： | IC DIGITAL PWR CONTROLLER 64QFN |
| 标准包装： | 50 |
| 应用： | 数字电源控制器 |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 12mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-QFN |
| 供应商设备封装： | 64-QFN 裸露焊盘（9x9） |
| 包装： | 管件 |
| 产品目录页面： | 2739 (CN2011-ZH PDF) |
| 其它名称： | 179-2417 |
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ZM7300G Series Digital Power Manager
Data Sheet
The ACFAIL_N and RES_N inputs should be controlled with open collector devices. The propagation
delay between the external device pulling the input low and the DPM pulling down OK lines and
triggering the turn-off process is approximately 1ms.
10.6.2 Front End Enable
The FE_EN pin is dedicated to the control of a DC-DC Front End. The Front End is typically used to
convert the 48V into the intermediate bus voltage (IBV). If the DPM is powered from an auxiliary
source, not from the IBV, it can control the DC-DC Front End.
When FE_EN is internally pulled up to 3.3V, the Front End is enabled. The FE_EN output can provide
up to 5mA of current. When the FE_EN goes low, the Front End is disabled. The Front End can be
enabled and disabled via the GUI IBS Monitoring Window or directly via the I 2 C bus using specific
commands.
The FE_EN pin should not be directly connected to the Enable pin of the DC-DC Front End. Typically,
the Enable pin is referenced to the primary side of the Front End that is isolated from the low voltage
secondary side. In addition, the Enable pin can be pulled up internally to a voltage potentially damaging
to the DPM FE_EN output. The best method is to interface the DPM with the Front End through an
optocoupler as shown in Figure 20. This configuration provides interface for negative logic front ends.
DPM
FE_EN
GND
3.3k
R
Q
Front End
Enable
-VIN
Figure 20. Interface Between DPM and DC-DC Front End
10.6.3 Crowbar
When the crowbar protection is enabled, the CB pin is internally pulled up to 3.3V for 1ms. It is capable
of supplying 5mA to turn on a crowbar circuit.
10.6.4 HRES_N
The HRES_N is an active low digital input. When it is pulled low, the DPM will perform full hardware
reset including processor, memory, and communication interface. The POL converters and auxiliary
devices will be turned off although sequencing and tracking during the turn-off are not guaranteed.
Communication with a host processor or GUI (if established) will be lost. When the input is released,
the DPM will first program all POL converters and then turn them on, if the Auto Turn-On is enabled.
Unlike all other I/O pins on the ZM7300 DPM, the HRES_N does not have an internal ESD protection
diode connected to VDD. Therefore, it is necessary to add the diode externally as shown in Figure 3.
ZD-00896 Rev. 5.1, 13-Jul-10
www.power-one.com
Page 26 of 33
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ZM7316G65503-B1 | 制造商:Power-One 功能描述:Digital Power Manager 64-Pin QFN EP Tube |
| ZM7316G-65503-B2 | 功能描述:PMIC 解决方案 50 pcs RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
| ZM7316G-65503-Q1 | 制造商:Power-One 功能描述:- Tape and Reel |
| ZM7316G-65503-R1 | 制造商:Power-One 功能描述:- Tape and Reel |
| ZM7316G-65503-T1 | 功能描述:PMIC 解决方案 500 pcs RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
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