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| 型号： | 05F6950 |
| 英文描述： | IC-COMPUTATION CIRCUIT |
| 中文描述： | 集成电路计算电路 |
| 文件页数： | 9/12页 |
| 文件大小： | 347K |
| 代理商： | 05F6950 |
AD524
REV. C
–6–
Figure 26. Large Signal Pulse Response and Settling Time
G = 1000
+Vs
RG2
7
16
8
–Vs
13
12
11
3
2
1
AD524
DUT
3
8
2
1
AD712
6
1/2
9.09k
1k
100
16.2k
5
6
7
4
1/2
9
+Vs
–Vs
16.2k
1F
1.62M
1.82k
10
100
1000
10
1F
G1, 10, 100
G1000
Figure 28. Noise Test Circuit
the gain bandwidth product which is determined by C3 or C4
and the input transconductance, reaches 25 MHz. Third, the in-
put voltage noise reduces to a value determined by the collector
current of the input transistors for an RTI noise of 7 nV/
√Hz at
G = 1000.
INPUT PROTECTION
As interface amplifiers for data acquisition systems, instrumen-
tation amplifiers are often subjected to input overloads, i.e.,
voltage levels in excess of the full scale for the selected gain
range. At low gains, 10 or less, the gain resistor acts as a current
limiting element in series with the inputs. At high gains the
lower value of RG will not adequately protect the inputs from
excessive currents. Standard practice would be to place series
limiting resistors in each input, but to limit input current to be-
low 5 mA with a full differential overload (36 V) would require
over 7k of resistance which would add 10 nV
√Hz of noise. To
provide both input protection and low noise a special series pro-
tect FET was used.
A unique FET design was used to provide a bidirectional cur-
rent limit, thereby, protecting against both positive and negative
overloads. Under nonoverload conditions, three channels CH2,
CH3, CH4, act as a resistance (
≈1 k) in series with the input as
before. During an overload in the positive direction, a fourth
channel, CH1, acts as a small resistance (≈3 k) in series with
the gate, which draws only the leakage current, and the FET
limits IDSS. When the FET enhances under a negative overload,
the gate current must go through the small FET formed by CH1
and when this FET goes into saturation, the gate current is lim-
ited and the main FET will go into controlled enhancement.
The bidirectional limiting holds the maximum input current to
3 mA over the 36 V range.
SETTLING TIME – s
080
20
40
60
–12 TO 12
4 TO –4
8 TO –8
12 TO –12
–8 TO 8
–4 TO 4
OUTPUT
STEP – V
1%
0.1%
0.01%
1%
0.1%
0.01%
70
10
30
50
Figure 25. Settling Time Gain = 1000
7
16
8
–Vs
INPUT
20V p-p
9
10
6
13
12
11
3
2
1
100k
0.1%
+Vs
10k
0.01%
1k
10T
10k
0.1%
AD524
1k
0.1%
100
0.1%
11k
0.1%
G = 10
G = 100
G = 1000
RG2
RG1
VOUT
Figure 27. Settling Time Test Circuit
+Vs
I2
50A
I1
50A
C4
C3
R53
20k
R54
20k
R52
20k
R55
20k
CH1
+IN
REFERENCE
SENSE
A3
I4
50A
I3
50A
–IN
CH2, CH3,
CH4
CH1
Q1, Q3
Q2, Q4
R57
20k
R56
20k
A1
A2
VB
RG1
RG2
4.44k
404
40
G100
G1000
–Vs
Vo
CH2, CH3,
CH4
Figure 29. Simplified Circuit of Amplifier; Gain is Defined as
((R56 + R57)/(RG) + 1. For a Gain of 1, RG is an Open Circuit
Theory of Operation
The AD524 is a monolithic instrumentation amplifier based on
the classic 3 op amp circuit. The advantage of monolithic con-
struction is the closely matched components that enhance the
performance of the input preamp. The preamp section develops
the programmed gain by the use of feedback concepts. The pro-
grammed gain is developed by varying the value of RG (smaller
values increase the gain) while the feedback forces the collector
currents Q1, Q2, Q3 and Q4 to be constant which impresses the
input voltage across RG.
As RG is reduced to increase the programmed gain, the trans-
conductance of the input preamp increases to the transconduct-
ance of the input transistors. This has three important advan-
tages. First, this approach allows the circuit to achieve a very
high open loop gain of 3
× 108 at a programmed gain of 1000
thus reducing gain related errors to a negligible 30ppm. Second,
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