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参数资料
型号： 0W344-005-XTP
厂商： ON SEMICONDUCTOR
元件分类： 数字信号处理
英文描述： BelaSigna 200 - Single-Chip Audio Processing System; Package: 52 PIN QFN 8x8; No of Pins: 52; Container: Tape and Reel; Qty per Container: 1000
中文描述： 0-BIT, 33 MHz, MIXED DSP, QCC52
封装： 8 X 8 MM, QFN-52
文件页数： 11/43页
文件大小： 1426K
代理商： 0W344-005-XTP
BelaSigna 200
Table 7: Instruction Set Continued
Instruction
Description
Instruction
Description
LDLC0/1 SIMM
Load loop counter with 8-bit unsigned
SIMM
PUSH IMM [,B]
Push IMM on stack
LDSI A, SIMM
Load A with signed SIMM
REP n
Repeat next instruction n+1 times
(9-bit unsigned)
LDSI Rij, SIMM
Load pointer register with unsigned
SIMM
REP Reg
Repeat next instruction Reg+1 times
MLD (Rj), (Ri) [,SQ]
Multiplier load and clear A
REP (Rij)
Repeat next instruction (Rij)+1 times
MLD Reg, (Ri) [,SQ]
Multiplier load and clear A
RES Reg, Bit
Clear bit in register
MODR Rj, Ri
Pointer register modification
RES (Rij), Bit
Clear bit in memory
MPYA (Rj), (Ri) [,SQ]
Multiplier load and accumulate
RET [B]
Return from subroutine
MPYA Reg, (Ri) [,SQ]
Multiplier load and accumulate
RND A
Round A with AL
MPYS (Rj), (Ri) [,SQ]
Multiplier load and accumulate
negative
SET Reg, Bit
Set bit in register
MPYS Reg, (Ri) [,SQ]
Multiplier load and accumulate
negative
SET (Rij), Bit
Set bit in memory
MSET (Rj), (Ri) [,SQ]
Multiplier load
SET_IE
Set interrupt enable flag
MSET Reg, (Ri) [,SQ]
Multiplier load
SHFT n
Shift A by +/- n bits (6-bit signed)
MUL [Cond] [,A] [,P]
Update A and/or PH | PL with X*Y on
condition
SHFT A [,Cond] [,INV]
Shift A by EXP bits on condition
NEG A [,Cond] [,DW]
Calculate negative value of A on
condition
SLEEP [IE]
Sleep
NOP
No operation
SUB A, Reg [,C]
Subtract register from A
OR A, Reg
OR register with AH to AH
SUB A, (Rij) [,C]
Subtract memory from A
OR A, (Rij)
OR memory with AH to AH
SUB A, DRAM [,B]
Subtract (DRAM) from A
OR A, DRAM [,B]
OR (DRAM) with AH to AH
SUB A, (Rij)p [,C]
Subtract program memory from A
OR A, (Rij)p
OR program memory with AH to AH
SUB A, Rc [,C]
Subtract Rc register from A
OR A, Rc
OR Rc register with AH to AH
SUBI A, IMM [,C]
Subtract IMM from A
ORI A, IMM
OR IMM with AH to AH
SUSI A, SIMM
Subtract signed SIMM from A
ORSI A, SIMM
OR unsigned SIMM with AH to AH
SWAP A [,Cond]
Swap AH, AL on condition
POP Reg [,B]
Pop register from stack
TGL Reg, Bit
Toggle bit in register
POP Rc [,B]
Pop Rc register from stack
TGL (Rij), Bit
Toggle bit in memory
PUSH Reg [,B]
Push register on stack
TST Reg, Bit
Test bit in register
PUSH Rc [,B]
Push Rc register on stack
TST (Rij), Bit
Test bit in memory
Table 8: Notation
Symbol
Meaning
Symbol
Meaning
A
B
Accumulator update
Memory bank selection (X or Y)
INV
Inverse shift
C
Carry bit
P
PRAM
PH | PL update
Program memory address (16 bits)
Cond
Condition in status register
Rc
Rc register (R0..7, PCFG0..2, PCFG4..6, LC0/1)
DRAM
Low data (X or Y) memory address (8 bits)
Reg
Data register (AL, AH, X, Y, ST, PC, PL, PH, EXT0, EXP, AE,
EXT3..EXT7)
DW
Double word
Ri / Rj / Rij
Pointer to X / Y / either data memory
IE
Interrupt enable flag
SIMM
Short immediate data (10 bits)
IMM
Immediate data (16 bits)
SQ
Square
Rev. 16 | Page 19 of 43 | www.onsemi.com
相关PDF资料
PDF描述
0W588-002-XUA BelaSigna 200 - Single-Chip Audio Processing System; Package: WLCSP 40, 3.8x2.3; No of Pins: 40; Container: Tape and Reel; Qty per Container: 5000
0W633-001-XTP BelaSigna 250 - 16 bit Audio Processor, Full Stereo 2-in, 2-out; Package: LFBGA 57, 5x5; No of Pins: 57; Container: Tape and Reel; Qty per Container: 5000
0W888-002-XTP BelaSigna 250 - 16 bit Audio Processor, Full Stereo 2-in, 2-out; Package: LFBGA 64, 7x7; No of Pins: 64; Container: Tape and Reel; Qty per Container: 1500
0X860 OSCILLOSCOPE 100MHz ANALOGUE
2-5174339-5 68 CONTACT(S), MALE, STRAIGHT TELECOM AND DATACOM CONNECTOR, SOLDER
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