参数资料
| 型号： | 101-0814 |
| 厂商： | Rabbit Semiconductor |
| 文件页数： | 21/94页 |
| 文件大小： | 0K |
| 描述： | COMPUTER SNG BD BL1810 512K SRAM |
| 标准包装： | 10 |
| 系列： | SBC |
| 模块/板类型： | 单板计算机模块 |
| 适用于相关产品： | BL1810 |
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24
Jackrabbit (BL1800)
It is very easy to do pulse-width modulation with the Rabbit 2000 microprocessor because
of the chip’s architecture.
3.4.1 DA1
The op amp supporting DA1 converts pulse-width modulated signals to an analog voltage
between 0 V and 5 V. A digital signal that varies with time is fed from PD4. The resolution
of the DA1 output depends on the smallest increment of time to change the on/off time
(the time between 5 V and 0 V). The Jackrabbit uses the Rabbit 2000’s Port D control reg-
isters to clock out the signal at a timer timeout. The timer used is timer B. Timer B has 10
bits of resolution so that the voltage can be varied in 1/1024 increments. The resolution is
thus about 5 mV (5 V/1024).
R28 is present solely to balance the op amp input current bias. R25 helps to achieve a volt-
age close to ground for a 0% duty cycle.
A design constraint dictates how fast timer B must run. The hardware filter has a resistor-
capacitor filter that averages the 0 V and 5 V values. Its effect is to smooth out the digital
pulse train. It cannot be perfect, and so there will be some ripple in the output voltage. The
maximum signal decay between pulses will occur when DA1 is set to 2.5 V. This means
the pulse train will have a 50% duty cycle. The maximum signal decay will be
where RC = 0.01 s for 14.74 MHz Jackrabbits, and t is the pulse on or off time (not the
length of the total cycle).
Timer B is driven at the Rabbit 2000 frequency divided by 2. The frequency achievable
with a 14.74 MHz clock is (14.74 MHz/2)/1024 = 7.17 kHz. This is a period of 1/f = 139 s.
For a 50% duty cycle, half of the period will be high (70 s at 5 V), and half will be low
(70 s at 0 V). Thus, a 14.74 MHz Jackrabbit has t = 70 s. Based on the standard capaci-
tor discharge formula, this means that the maximum voltage change will be
This is less than a 20 mV peak-to-peak ripple.
The DA1 output can be less than 100 mV for a 0% duty cycle and above 3.5 V for a 100%
duty cycle. Because of software limitations on the low side and hardware limitations on
the high side, the duty cycle can only be programmed from 12% to 72%. The low limita-
tion allows the software to perform other tasks as well as maintain the PWM for the D/A
converters. The high limitation is simply the maximum voltage obtainable with the
LM324 op amp used in the circuit. Anything outside the 12%–72% range gets output as
2.5 V
1
e
t
–
RC
--------
–
×
2.5 V
1
e
70 s
–
0.01 s
----------------
–
×
17.4 mV
=
相关PDF资料 |
PDF描述 |
|---|---|
| 101-1007 | MODULE POWERCORE FLEX 3810 |
| 101-1028 | MODULE RABBITCORE RCM3750 |
| 101-1087 | MODULE RABBITCORE RCM 3365 |
| 1B31AN | IC SIGNAL COND STRAIN GAGE 28DIP |
| 1B32AN | IC SIGNAL COND HYBRID 28-DIP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 101-0815 | 功能描述:单板计算机 SR9100 512K SRAM RoHS:否 制造商:Ampro By ADLINK 外观尺寸:EPIC 处理器类型:Intel Atom D510 频率:1.66 GHz 存储容量:2 GB (max) 存储类型:DDR2, L2 Cache 接口类型:Ethernet, PS/2, SATA, Serial, USB 工作电源电压:5 V, 12 V 功耗:13 W 最大工作温度:+ 70 C 尺寸:165.1 mm x 114.3 mm |
| 101-0816 | 功能描述:KIT DEV RABBITCORE TCP/IP 2000 RoHS:否 类别:编程器，开发系统 >> 过时/停产零件编号 系列:* 标准包装:1 系列:- 类型:MCU 适用于相关产品:Freescale MC68HC908LJ/LK（80-QFP ZIF 插口） 所含物品:面板、缆线、软件、数据表和用户手册 其它名称:520-1035 |
| 101-0817 | 功能描述:单板计算机 BL2030 512K SRAM RoHS:否 制造商:Ampro By ADLINK 外观尺寸:EPIC 处理器类型:Intel Atom D510 频率:1.66 GHz 存储容量:2 GB (max) 存储类型:DDR2, L2 Cache 接口类型:Ethernet, PS/2, SATA, Serial, USB 工作电源电压:5 V, 12 V 功耗:13 W 最大工作温度:+ 70 C 尺寸:165.1 mm x 114.3 mm |
| 101-0818 | 功能描述:单板计算机 BL2100 Fric Lk 512K RoHS:否 制造商:Ampro By ADLINK 外观尺寸:EPIC 处理器类型:Intel Atom D510 频率:1.66 GHz 存储容量:2 GB (max) 存储类型:DDR2, L2 Cache 接口类型:Ethernet, PS/2, SATA, Serial, USB 工作电源电压:5 V, 12 V 功耗:13 W 最大工作温度:+ 70 C 尺寸:165.1 mm x 114.3 mm |
| 101-0820 | 功能描述:COMPUTER SGL-BD BL2000 SRAM/FLSH RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微控制器或微处理器模块 系列:SBC 产品目录绘图:DLP-245SY-G 标准包装:1 系列:USB 模块/板类型:开发板 适用于相关产品:USB 其它名称:813-1006 |
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