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参数资料
| 型号： | 1337DVGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | REAL TIME CLOCK, PDSO8 |
| 封装： | 3 MM, ROHS COMPLIANT, MSOP-8 |
| 文件页数： | 6/24页 |
| 文件大小： | 362K |
| 代理商： | 1337DVGI |
IDT1337
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
IDT REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
14
IDT1337
REV J 111009
Note 1: Limits at -40°C are guaranteed by design and are not production tested.
Note 2: SCL only.
Note 3: SDA, INTA, and SQW/INTB.
Note 4: ICCA—SCL clocking at maximum frequency = 400 kHz, VIL = 0.0V, VIH = VCC.
Note 5: Specified with the I2C bus inactive, VIL = 0.0V, VIH = VCC.
Note 6: SQW enabled.
Note 7: Specified with the SQW function disabled by setting INTCN = 1.
Note 8: Using recommended crystal on X1 and X2.
Note 9: The device is fully accessible when 1.8 < VCC < 5.5 V. Time and date are maintained when 1.3 V < VCC <
1.8 V.
Note 10: After this period, the first clock pulse is generated.
Note 11: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of
the SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 12: The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL
signal.
Note 13: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > to 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) +
tSU:DAT = 1000 + 250 = 1250 ns before the SCL line is released.
Note 14: CB—total capacitance of one bus line in pF.
Note 15: Guaranteed by design. Not production tested.
Rise Time of Both SDA and SCL
Signals, Note 14
tR
Fast Mode
20 + 0.1CB
300
ns
Standard Mode
20 + 0.1CB
1000
Fall Time of Both SDA and SCL Signals,
Note 14
tF
Fast Mode
20 + 0.1CB
300
ns
Standard Mode
20 + 0.1CB
300
Setup Time for STOP Condition
tSU:STO
Fast Mode
0.6
s
Standard Mode
4.0
Capacitive Load for Each Bus Line,
Note 14
CB
400
pF
I/O Capacitance (SDA, SCL)
CI/O
Note 15
10
pF
32.768 kHz Clock Accuracy with
External Crystal
TA=25°C
VCC=3.3 V
±10
ppm
32.768 kHz Clock Accuracy with
Internal Crystal
TA=25°C
VCC=3.3 V
(crystal accuracy
±20ppm)
±30
ppm
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 1337DVGI8 | 制造商:Integrated Device Technology Inc 功能描述:REAL TIME CLOCK SERL 8TSSOP - Tape and Reel |
| 1337G0 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Peripheral IC |
| 1337G1 | 功能描述:重负荷电源连接器 PCB45 HORIZ (TOP) RA LP CONT. RoHS:否 制造商:Hirose Connector 系列:PS2 产品类型:Connectors 位置/触点数量: 端接类型:Crimp 触点材料: 触点电镀:Gold 电压额定值: 电流额定值:300 A 附件类型: |
| 1337G2 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Peripheral IC |
| 1337GCSRI | 功能描述:实时时钟 实时时钟 with Embedded Crystal RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
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