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| 型号： | 18495 |
| 英文描述： | Microprocessor Family Phase Lock Loop (PLL) Clock Control Application Note? 68.1KB (PDF) |
| 中文描述： | 微处理器家族锁相环（PLL）的时钟控制应用指南？ 68.1KB（PDF格式） |
| 文件页数： | 1/2页 |
| 文件大小： | 68K |
| 代理商： | 18495 |
Publication #: 18495 Rev. D Amendment/0
Issue Date: August 1995
This document contains information on a product under development at Advanced Micro Devices. The information is
intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Advanced
Micro
Devices
Phase Lock Loop (PLL) Clock Control
Application Note
Significant system power savings can be achieved by using the Phase Lock Loop (PLL) clock control circuit outlined
in this application note with any Am486 or Am5X86 family microprocessor.
The Environmental Protection Agency’s (EPA) Energy
Star program, unveiled during the summer of 1992, pro-
vided the personal computer (PC) industry with a vol-
untary
incentive
to
reduce
desktop
PC
power
consumption. The prime directive of the EPA’s Energy
Star program is that no more than 30 W will be con-
sumed in low power mode for each of the following sys-
tem components: the personal computer itself, the
monitor, and the printer.
The Am486DX2-80 microprocessor serves as an exam-
ple in this application note, illustrating how the Phase
Lock Loop clock control circuit can enable your design
to include an efficient and energy-saving clock control
mechanism.
Power Consumption
The CPU accounts for a significant part of system power
consumption. The data sheet typical ICC for the 3.3-V
Am486DX2-80 microprocessor is 640 mA, which trans-
lates to a typical power consumption of 2.1 W.
Using the simple Phase Lock Loop (PLL) clock control
circuit with any member of the Am486 or Am5X86 mi-
croprocessor family enables system power consump-
tion to be significantly lowered. This feature assists
designers in meeting the Energy Star requirements.
A typical motherboard, including an Am486DX2-80
CPU, consumes around 13 W, meaning that the CPU
accounts for approximately 16 percent of the total moth-
erboard power consumption. By controlling the clock,
via the methods described in this application note, the
CPU component of the motherboard power consump-
tion can be reduced by approximately 90 percent (See
Table 1). Overall motherboard power consumption is
also lowered by the reduced clock speed.
Figure 1.
Phase Lock Loop (PLL) Clock Control Circuit
Note: This circuit may not be appropriate for all motherboard designs. To maintain proper system operation, ensure
all other system clocks conform to required specifications when implementing this circuit in a design.
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