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| 型号： | 18495 |
| 英文描述： | Microprocessor Family Phase Lock Loop (PLL) Clock Control Application Note? 68.1KB (PDF) |
| 中文描述： | 微处理器家族锁相环（PLL）的时钟控制应用指南？ 68.1KB（PDF格式） |
| 文件页数： | 2/2页 |
| 文件大小： | 68K |
| 代理商： | 18495 |
AMD
2
Phase Lock Loop (PLL) Clock Control
SLOWCLK For Power Savings
Because Phase Lock Loop clocks are not static, they
may not be turned off or driven at a frequency less than
8 MHz. Furthermore, the frequency of the CPU clock
cannot be changed more than 0.1 percent cycle-to-cy-
cle per the data sheet specification. The designer must
ensure this specification is met or the PLL will lose its
lock and unstable operation will result.
The SLOWCLK signal is common to all three of the
74F00 NAND gates, and is normally High. Following a
user-defined time-out, SLOWCLK is driven Low by any
control line. With SLOWCLK Low, the outputs of all
three of the 74F00 NAND gates are High, which selects
an output frequency of 8 MHz from the frequency gen-
erator. Once activity is detected, SLOWCLK goes High,
reselecting the full-on frequency. (See Figure 1).
SLOWCLK CONTROL
The AV9154-04 slowly ramps the CPU clock down to 8
MHz and may be driven by any general purpose output,
or any other control line.
One solution is to use this clock control solution with
Phoenix Technologies’ Multikey/42G energy-efficient
keyboard controller. Implement the Multikey/42G solu-
tion by replacing the system’s standard 8042 keyboard
controller with the Mulitkey/42G. Available in either a
40-pin Dual In-line package (DIP) or 44-pin Plastic
Leaded Chip Carrier (PLCC) package, the Multikey/42G
solution uses one of the unused 8042 port signals, (P1.1
to P1.7, or P2.0 to P2.3), to control the SLOWCLK
signal.
Once the Multikey/42G keyboard controller is config-
ured, Phoenix Technologies’ FOCUS utility, provided as
part of this solution, runs as a standard or TSR utility.
The FOCUS utility permits refinements to the initial con-
figuration, such as timer settings, which turn off the hard
disk(s) after a period of inactivity.
POWER SAVINGS
Clock control solutions, evaluated in the Advanced Mi-
cro Devices laboratory, have shown significant power
savings of over 4 W. Placing a power-managed hard
disk drive in standby mode can account for an additional
system power savings of 2.2 W, resulting in a total pos-
sible system savings of 6.2 W.
Note: Care should be taken when slowing the CPU
clock in systems where other clocks are derivatives of
the CPU clock. The designer must ensure that all sys-
tem timing requirements are maintained when changing
the frequency of the clock to the microprocessor.
For more information or to order literature:
Advanced Micro Devices, Inc.
5204 East Ben White Blvd.
Mail Stop 604
Austin, Texas 78741
(800) 222-9323
(512) 602-5651
Table 1. ICC Values for Am486DX-80 CPU (VCC=3.3 V)
Operating Frequency
Typical Power Supply
Current (I
CC)
8 MHz
(SLOWCLK)
64 mA
80 MHz
640 mA
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