参数资料
型号: 19077
元件分类: 模拟信号调理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO28
封装: SOIC-28
文件页数: 3/8页
文件大小: 366K
代理商: 19077
Vicor Corp. Tel: 800-735-6200, 978-470-2900 Fax: 978-475-6715
PAC, Phased Array Controller
Rev. 1.2
Page 3 of 8
Set your site on VICOR at vicorpower.com
PC 1-12 (PRIMARY CONTROL): The Primary
Control (PC) pin is also a bidirectional port. In addition to
communicating module status information, the PAC can
receive power from a module array’s PC pins, eliminating
the need for a separate external 5 V power supply
referenced to the primary side of the converters. The PAC
may require up to 1.5 mA supply current per operating
module depending on operating frequency, as illustrated in
figures 5a, 5b, and 5c. In all configurations, the PC pin is
also used as a logic input to inform the PAC that a
converter module is operating on the corresponding
channel. When the interfaced converter is operating
properly, PC assumes the high state. If a fault occurs within
a converter, it’s PC pin goes low, the module is shutoff, and
the PAC is notified. The PAC responds by reconfiguring the
sync pulse decoding logic in order to adjust the sync pulse
sequence. The voltage on the PC pin delivered by the
module is 5.9 V +/- 200 mV during normal operation. The
low, or fault state PC voltage is less than 0.5 V. While the
SYSTEM RESET input of the PAC is held low, the PC pin
is driven low with active pull down and will sink the
maximum current available from the associated converter.
The PAC internal circuitry receives current from all PC pins
via a diode “OR” of all PC signals, which serves as internal
Vcc. Similar to the PR pins, the PAC’s PC pins utilize
Schmitt triggers for noise immunity.
OK: The OK pin is a multifunction I/O pin used as a flag
signal to indicate normal or abnormal operation, and to
reset the PAC chip after a fault is detected. It’s normal
active low state is achieved with a driver capable of sinking
5 mA (to illuminate a green LED, for example). During a
fault, OK is in the high state with internal pull up limited to
5 A. When the fault is detected, the internal latch can be
reset by forcing the OK pin low via an external switch.
Similar in nature to the PR pin, the OK pin employs
Schmitt triggers as buffers.
Ipc Current Per Module Vs. PR Frequency
Where N = # of Modules
0
0.5
1
1.5
2
10 kHz
20 kHz
50 kHz
100 kHz
200 kHz
500 kHz
1 MHz
Ipc
C
u
rrent
P
er
Mod
u
le
(mA)
3
6
9
12
3
6
9
12
PR Frequency
Icc current Vs. PR Frequency (N=3,6,9,12)
Where N= # of modules
0
5
10
15
20
10 kHz
20 kHz
50 kHz
100 kHz
200 kHz
500 kHz
1 MHz
Icc
(mA)
12
3
9
6
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
10 kHz
20 kHz
50 kHz
100 kHz
200 kHz
500 kHz
1 MHz
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
Icc
for
N=1
(mA)
Icc
for
N=1
(mA)
PR Frequency (Hz)
Figure 5b: Icc current Vs. PR Frequency (N=3,6,9,12 modules)
Figure 5a: Ipc current per module vs. PR frequency
Where N = # of modules
Figure 5c: Average current Icc for N=1 Vs. PR frequency
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